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Searched refs:Tmp3 (Results 1 – 12 of 12) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DIntrinsicLowering.cpp73 Value *Tmp3 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
79 Tmp3 = Builder.CreateAnd(Tmp3, in LowerBSWAP()
85 Tmp4 = Builder.CreateOr(Tmp4, Tmp3, "bswap.or1"); in LowerBSWAP()
101 Value* Tmp3 = Builder.CreateLShr(V, in LowerBSWAP() local
126 Tmp3 = Builder.CreateAnd(Tmp3, in LowerBSWAP()
136 Tmp4 = Builder.CreateOr(Tmp4, Tmp3, "bswap.or3"); in LowerBSWAP()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp1804 SDValue Tmp3 = Node->getOperand(2); in ExpandDYNAMIC_STACKALLOC() local
1814 Align Alignment = cast<ConstantSDNode>(Tmp3)->getAlignValue(); in ExpandDYNAMIC_STACKALLOC()
3088 SDValue Tmp1, Tmp2, Tmp3, Tmp4; in ExpandNode() local
4151 Tmp3 = Node->getOperand(2); in ExpandNode()
4154 Tmp2, Tmp3, in ExpandNode()
4159 Tmp2, Tmp3, ISD::SETNE); in ExpandNode()
4221 Tmp3 = Tmp2; in ExpandNode()
4223 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2, in ExpandNode()
4226 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
4227 DAG.getConstant(0, dl, Tmp3.getValueType()), in ExpandNode()
[all …]
H A DTargetLowering.cpp8361 SDValue Tmp2, Tmp3; in expandShiftParts() local
8364 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt); in expandShiftParts()
8367 Tmp3 = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt); in expandShiftParts()
8379 Hi = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp3, Tmp2); in expandShiftParts()
8380 Lo = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp1, Tmp3); in expandShiftParts()
8382 Lo = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp3, Tmp2); in expandShiftParts()
8383 Hi = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp1, Tmp3); in expandShiftParts()
9335 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5; in expandVPCTPOP() local
9346 Tmp3 = DAG.getNode(ISD::VP_AND, dl, VT, in expandVPCTPOP()
9350 Op = DAG.getNode(ISD::VP_ADD, dl, VT, Tmp2, Tmp3, Mask, VL); in expandVPCTPOP()
[all …]
H A DLegalizeFloatTypes.cpp2344 SDValue Tmp1, Tmp2, Tmp3, OutputChain; in FloatExpandSetCCOperands() local
2351 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); in FloatExpandSetCCOperands()
2360 NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3); in FloatExpandSetCCOperands()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DIntegerDivision.cpp125 Value *Tmp3 = Builder.CreateXor(Tmp1, Divisor); in generateSignedDivisionCode() local
126 Value *U_Dvsr = Builder.CreateSub(Tmp3, Tmp1); in generateSignedDivisionCode()
262 Value *Tmp3 = Builder.CreateLShr(Dividend, SR_1); in generateUnsignedDivisionCode() local
330 R_1->addIncoming(Tmp3, Preheader); in generateUnsignedDivisionCode()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp4256 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchBEXTRFromAndImm() local
4257 if (tryFoldLoad(Node, N0.getNode(), Input, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in matchBEXTRFromAndImm()
4259 Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Control, Input.getOperand(0)}; in matchBEXTRFromAndImm()
4293 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPISTR() local
4294 if (MayFoldLoad && tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPISTR()
4295 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPISTR()
4326 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPESTR() local
4327 if (MayFoldLoad && tryFoldLoad(Node, N2, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPESTR()
4328 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPESTR()
4619 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchVPTERNLOG() local
[all …]
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGExprComplex.cpp1093 llvm::Value *Tmp3 = Builder.CreateAdd(Tmp1, Tmp2); // ac+bd in EmitBinDiv() local
1104 DSTr = Builder.CreateUDiv(Tmp3, Tmp6); in EmitBinDiv()
1107 DSTr = Builder.CreateSDiv(Tmp3, Tmp6); in EmitBinDiv()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp2104 Register Tmp3 = MRI.createVirtualRegister(RC); in prepareSymbol() local
2112 BuildMI(MBB, I, DL, TII->get(VE::LEASLrri), Tmp3) in prepareSymbol()
2117 .addReg(Tmp3, getKillRegState(true)) in prepareSymbol()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp3276 SDValue Tmp3 = ST->getValue(); in LowerSTOREi1() local
3277 assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only"); in LowerSTOREi1()
3278 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3); in LowerSTOREi1()
3280 DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), MVT::i8, in LowerSTOREi1()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp2503 SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, IntTy, Tmp2, Rup); in emitHvxShiftRightRnd() local
2508 SDValue Tmp5 = DAG.getNode(ShRight, dl, IntTy, {Tmp3, One}); in emitHvxShiftRightRnd()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp2466 SDValue Tmp3 = in lowerVAARG() local
2471 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, in lowerVAARG()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp9264 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); in LowerSHL_PARTS() local
9265 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); in LowerSHL_PARTS()
9293 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); in LowerSRL_PARTS() local
9294 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRL_PARTS()
9321 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); in LowerSRA_PARTS() local
9322 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRA_PARTS()