| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 4190 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchBEXTRFromAndImm() local
4191 if (tryFoldLoad(Node, N0.getNode(), Input, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in matchBEXTRFromAndImm()
4193 Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Control, Input.getOperand(0)}; in matchBEXTRFromAndImm()
4227 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPISTR() local
4228 if (MayFoldLoad && tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPISTR()
4229 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPISTR()
4260 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPESTR() local
4261 if (MayFoldLoad && tryFoldLoad(Node, N2, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPESTR()
4262 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPESTR()
4553 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchVPTERNLOG() local
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| H A D | X86ISelLowering.cpp | 37678 unsigned Tmp0 = SrcBits, Tmp1 = SrcBits; in ComputeNumSignBitsForTargetNode() local
37680 Tmp0 = NumSignBitsPACKSS(Op.getOperand(0), DemandedLHS); in ComputeNumSignBitsForTargetNode()
37683 unsigned Tmp = std::min(Tmp0, Tmp1); in ComputeNumSignBitsForTargetNode()
37733 unsigned Tmp0 = in ComputeNumSignBitsForTargetNode() local
37735 if (Tmp0 == 1) return 1; // Early out. in ComputeNumSignBitsForTargetNode()
37738 return std::min(Tmp0, Tmp1); in ComputeNumSignBitsForTargetNode()
37742 unsigned Tmp0 = DAG.ComputeNumSignBits(Op.getOperand(0), Depth+1); in ComputeNumSignBitsForTargetNode() local
37743 if (Tmp0 == 1) return 1; // Early out. in ComputeNumSignBitsForTargetNode()
37745 return std::min(Tmp0, Tmp1); in ComputeNumSignBitsForTargetNode()
37782 unsigned Tmp0 = VTBits; in ComputeNumSignBitsForTargetNode() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUPromoteAlloca.cpp | 1480 Value *Tmp0 = Builder.CreateMul(TCntY, TCntZ, "", true, true); in tryPromoteAllocaToLDS() local
1481 Tmp0 = Builder.CreateMul(Tmp0, TIdX); in tryPromoteAllocaToLDS()
1483 Value *TID = Builder.CreateAdd(Tmp0, Tmp1); in tryPromoteAllocaToLDS()
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| H A D | AMDGPUISelLowering.cpp | 2434 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not); in LowerFTRUNC() local
2444 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); in LowerFTRUNC()
5844 unsigned Tmp0 = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1); in ComputeNumSignBitsForTargetNode() local
5845 if (Tmp0 == 1) in ComputeNumSignBitsForTargetNode()
5848 return std::min({Tmp0, Tmp1, Tmp2}); in ComputeNumSignBitsForTargetNode()
5882 unsigned Tmp0 = Analysis.computeNumSignBits(Src0, DemandedElts, Depth + 1); in computeNumSignBitsForTargetInstr() local
5883 if (Tmp0 == 1) in computeNumSignBitsForTargetInstr()
5885 return std::min({Tmp0, Tmp1, Tmp2}); in computeNumSignBitsForTargetInstr()
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| H A D | AMDGPULegalizerInfo.cpp | 2543 auto Tmp0 = B.buildAnd(S64, Src, Not); in legalizeIntrinsicTrunc() local
2549 auto Tmp1 = B.buildSelect(S64, ExpLt0, SignBit64, Tmp0); in legalizeIntrinsicTrunc()
4861 auto Tmp0 = B.buildFMA(ResTy, NegY, R, One); in legalizeFastUnsafeFDIV64() local
4862 R = B.buildFMA(ResTy, Tmp0, R, R); in legalizeFastUnsafeFDIV64()
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| H A D | SIISelLowering.cpp | 10514 SDValue Tmp0 = DAG.getNode(ISD::FMA, SL, VT, NegY, R, One); in lowerFastUnsafeFDIV64() local
10516 R = DAG.getNode(ISD::FMA, SL, VT, Tmp0, R, R); in lowerFastUnsafeFDIV64()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | IntegerDivision.cpp | 234 Value *Tmp0 = Builder.CreateCall(CTLZ, {Divisor, True}); in generateUnsignedDivisionCode() local
236 Value *SR = Builder.CreateSub(Tmp0, Tmp1); in generateUnsignedDivisionCode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 503 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
504 Tmp0 = MRI.createVirtualRegister(MRI.getRegClass(InReg)); in LowerFPToInt()
515 Tmp0 = InReg; in LowerFPToInt()
517 BuildMI(BB, DL, TII.get(Abs), Tmp0).addReg(InReg); in LowerFPToInt()
521 BuildMI(BB, DL, TII.get(LT), CmpReg).addReg(Tmp0).addReg(Tmp1); in LowerFPToInt()
531 BuildMI(BB, DL, TII.get(GE), SecondCmpReg).addReg(Tmp0).addReg(Tmp1); in LowerFPToInt()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 6039 SDValue Tmp0 = Op.getOperand(0); in LowerFCOPYSIGN() local
6044 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST || in LowerFCOPYSIGN()
6045 Tmp0.getOpcode() == ARMISD::VMOVDRR; in LowerFCOPYSIGN()
6059 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); in LowerFCOPYSIGN()
6070 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); in LowerFCOPYSIGN()
6081 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot)); in LowerFCOPYSIGN()
6104 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32, in LowerFCOPYSIGN()
6105 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2); in LowerFCOPYSIGN()
6107 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1)); in LowerFCOPYSIGN()
6111 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 2461 auto [Tmp0, Ovf] = emitHvxAddWithOverflow(Inp, LowBits, dl, Signed, DAG); in emitHvxShiftRightRnd()
2465 SDValue Tmp2 = DAG.getNode(ShRight, dl, IntTy, Tmp0, AmtM1); in emitHvxShiftRightRnd()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 9184 SDValue Tmp0 = getValue(I.getArgOperand(0)); in visitBinaryFloatCall() local
9186 EVT VT = Tmp0.getValueType(); in visitBinaryFloatCall()
9187 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1, Flags)); in visitBinaryFloatCall()
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