| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVRedundantCopyElimination.cpp | 110 Register TargetReg = Cond[1].getReg(); in optimizeBlock() local
111 if (!TargetReg) in optimizeBlock()
126 TargetReg == DefReg) { in optimizeBlock()
138 if (MI->modifiesRegister(TargetReg, TRI)) in optimizeBlock()
149 assert(CondBr->getOperand(0).getReg() == TargetReg && "Unexpected register"); in optimizeBlock()
153 CondBr->clearRegisterKills(TargetReg, TRI); in optimizeBlock()
156 if (!MBB.isLiveIn(TargetReg)) in optimizeBlock()
157 MBB.addLiveIn(TargetReg); in optimizeBlock()
161 MMI.clearRegisterKills(TargetReg, TRI); in optimizeBlock()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 186 unsigned TargetReg = Inst.getOperand(1).getReg(); in emitInstruction() local
187 emitMask(TargetReg, IndirectBranchMaskReg, STI); in emitInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86SpeculativeLoadHardening.cpp | 991 unsigned TargetReg; in tracePredStateThroughIndirectBranches() local
1022 TargetReg = TI.getOperand(0).getReg(); in tracePredStateThroughIndirectBranches()
1042 TargetAddrSSA.AddAvailableValue(&MBB, TargetReg); in tracePredStateThroughIndirectBranches()
1109 Register TargetReg = MRI->createVirtualRegister(&X86::GR64RegClass); in tracePredStateThroughIndirectBranches() local
1114 TII->get(X86::MOV64ri32), TargetReg) in tracePredStateThroughIndirectBranches()
1122 TargetReg) in tracePredStateThroughIndirectBranches()
1134 TargetAddrSSA.AddAvailableValue(Pred, TargetReg); in tracePredStateThroughIndirectBranches()
1142 Register TargetReg = TargetAddrSSA.GetValueInMiddleOfBlock(&MBB); in tracePredStateThroughIndirectBranches() local
1153 .addReg(TargetReg, RegState::Kill) in tracePredStateThroughIndirectBranches()
1172 .addReg(TargetReg, RegState::Kill) in tracePredStateThroughIndirectBranches()
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| H A D | X86ExpandPseudo.cpp | 229 auto TargetReg = STI->getTargetTriple().isOSWindows() ? X86::RCX : X86::RDI; in expandCALL_RVMARKER() local
231 .addReg(TargetReg, RegState::Define) in expandCALL_RVMARKER()
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| H A D | X86ISelLowering.cpp | 59343 Register TargetReg; in EmitKCFICheck() local
59351 TargetReg = Target.getReg(); in EmitKCFICheck()
59360 TargetReg = X86::R11; in EmitKCFICheck()
59368 .addReg(TargetReg) in EmitKCFICheck()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZAsmPrinter.cpp | 331 Register TargetReg = MI->getOperand(0).getReg(); in emitInstruction() local
342 if (TargetReg != ADAReg) { in emitInstruction()
343 IndexReg = TargetReg; in emitInstruction()
347 MCInstBuilder(SystemZ::LLILF).addReg(TargetReg).addImm(Disp)); in emitInstruction()
351 MCInstBuilder(SystemZ::ALGFI).addReg(TargetReg).addImm(Disp)); in emitInstruction()
356 .addReg(TargetReg) in emitInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.h | 181 Register TargetReg) const;
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| H A D | AArch64FrameLowering.cpp | 794 Register TargetReg = RealignmentPadding in allocateStackSpace() local
798 emitFrameOffset(MBB, MBBI, DL, TargetReg, AArch64::SP, -AllocSize, &TII, in allocateStackSpace()
805 .addReg(TargetReg, RegState::Kill) in allocateStackSpace()
884 Register TargetReg = findScratchNonCalleeSaveRegister(&MBB); in allocateStackSpace() local
885 assert(TargetReg != AArch64::NoRegister); in allocateStackSpace()
887 emitFrameOffset(MBB, MBBI, DL, TargetReg, AArch64::SP, -AllocSize, &TII, in allocateStackSpace()
892 BuildMI(MBB, MBBI, DL, TII.get(AArch64::ANDXri), TargetReg) in allocateStackSpace()
893 .addReg(TargetReg, RegState::Kill) in allocateStackSpace()
899 .addReg(TargetReg); in allocateStackSpace()
4866 Register TargetReg) const { in inlineStackProbeLoopExactMultiple()
[all …]
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| H A D | AArch64InstrInfo.h | 537 Register TargetReg,
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| H A D | AArch64InstrInfo.cpp | 9540 Register TargetReg, bool FrameSetup) const { in probedStackAlloc() argument
9541 assert(TargetReg != AArch64::SP && "New top of stack cannot aleady be in SP"); in probedStackAlloc()
9571 .addReg(TargetReg) in probedStackAlloc()
9596 .addReg(TargetReg) in probedStackAlloc()
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| H A D | AArch64ISelLowering.cpp | 2938 Register TargetReg = MI.getOperand(0).getReg(); in EmitDynamicProbedAlloc() local
2940 TII.probedStackAlloc(MBBI, TargetReg, false); in EmitDynamicProbedAlloc()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFrameLowering.cpp | 179 Register TargetReg) { in buildGitPtr() argument
184 Register TargetLo = TRI->getSubReg(TargetReg, AMDGPU::sub0); in buildGitPtr()
185 Register TargetHi = TRI->getSubReg(TargetReg, AMDGPU::sub1); in buildGitPtr()
190 .addReg(TargetReg, RegState::ImplicitDefine); in buildGitPtr()
193 BuildMI(MBB, I, DL, GetPC64, TargetReg); in buildGitPtr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 866 Register TargetReg = I->getOperand(1).getReg(); in expandEhReturn() local
874 .addReg(TargetReg) in expandEhReturn()
877 .addReg(TargetReg) in expandEhReturn()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 3063 Register TargetReg = MI.getOperand(0).getReg(); in expandVSXMemPseudo() local
3065 if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) || in expandVSXMemPseudo()
3066 (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31)) in expandVSXMemPseudo()
3190 Register TargetReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
3191 if (PPC::VSFRCRegClass.contains(TargetReg)) { in expandPostRAPseudo()
3212 Register TargetReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
3213 if (PPC::VSFRCRegClass.contains(TargetReg)) in expandPostRAPseudo()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 214 const SmallSet<Register, 2> &TargetReg,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3656 Register TargetReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in selectBrJT() local
3660 {TargetReg, ScratchReg}, {JTAddr, Index}) in selectBrJT()
3666 MIB.buildInstr(AArch64::BR, {}, {TargetReg}); in selectBrJT()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 3333 Register TargetReg, Register InsertReg, in buildBitFieldInsert() argument
3335 LLT TargetTy = B.getMRI()->getType(TargetReg); in buildBitFieldInsert()
3349 auto MaskedOldElt = B.buildAnd(TargetTy, TargetReg, InvShiftedMask); in buildBitFieldInsert()
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