| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVRedundantCopyElimination.cpp | 106 Register TargetReg = Cond[1].getReg(); in optimizeBlock() local
107 if (!TargetReg) in optimizeBlock()
122 TargetReg == DefReg) { in optimizeBlock()
134 if (MI->modifiesRegister(TargetReg, TRI)) in optimizeBlock()
145 assert(CondBr->getOperand(0).getReg() == TargetReg && "Unexpected register"); in optimizeBlock()
149 CondBr->clearRegisterKills(TargetReg, TRI); in optimizeBlock()
152 if (!MBB.isLiveIn(TargetReg)) in optimizeBlock()
153 MBB.addLiveIn(TargetReg); in optimizeBlock()
157 MMI.clearRegisterKills(TargetReg, TRI); in optimizeBlock()
|
| H A D | RISCVFrameLowering.cpp | 616 Register TargetReg = RISCV::X6; in allocateAndProbeStackForRVV() local
618 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoReadVLENB), TargetReg) in allocateAndProbeStackForRVV()
620 TII->mulImm(MF, MBB, MBBI, DL, TargetReg, NumOfVReg, Flag); in allocateAndProbeStackForRVV()
625 CFIBuilder.buildDefCFA(TargetReg, -Amount); in allocateAndProbeStackForRVV()
630 .addReg(TargetReg); in allocateAndProbeStackForRVV()
640 .addReg(TargetReg) in allocateAndProbeStackForRVV()
813 Register TargetReg = RISCV::X6; in allocateStack() local
815 RI->adjustReg(MBB, MBBI, DL, TargetReg, SPReg, in allocateStack()
820 CFIBuilder.buildDefCFA(TargetReg, RoundedSize); in allocateStack()
824 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PROBED_STACKALLOC)).addReg(TargetReg); in allocateStack()
[all …]
|
| H A D | RISCVISelLowering.cpp | 24442 Register TargetReg = MI.getOperand(0).getReg(); in emitDynamicProbedAlloc() local
24478 .addReg(TargetReg) in emitDynamicProbedAlloc()
24484 .addReg(TargetReg) in emitDynamicProbedAlloc()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 185 MCRegister TargetReg = Inst.getOperand(1).getReg(); in emitInstruction() local
186 emitMask(TargetReg, IndirectBranchMaskReg, STI); in emitInstruction()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86SpeculativeLoadHardening.cpp | 989 Register TargetReg; in tracePredStateThroughIndirectBranches() local
1020 TargetReg = TI.getOperand(0).getReg(); in tracePredStateThroughIndirectBranches()
1040 TargetAddrSSA.AddAvailableValue(&MBB, TargetReg); in tracePredStateThroughIndirectBranches()
1106 Register TargetReg = MRI->createVirtualRegister(&X86::GR64RegClass); in tracePredStateThroughIndirectBranches() local
1111 TII->get(X86::MOV64ri32), TargetReg) in tracePredStateThroughIndirectBranches()
1119 TargetReg) in tracePredStateThroughIndirectBranches()
1131 TargetAddrSSA.AddAvailableValue(Pred, TargetReg); in tracePredStateThroughIndirectBranches()
1139 Register TargetReg = TargetAddrSSA.GetValueInMiddleOfBlock(&MBB); in tracePredStateThroughIndirectBranches() local
1150 .addReg(TargetReg, RegState::Kill) in tracePredStateThroughIndirectBranches()
1169 .addReg(TargetReg, RegState::Kill) in tracePredStateThroughIndirectBranches()
|
| H A D | X86ExpandPseudo.cpp | 227 auto TargetReg = STI->getTargetTriple().isOSWindows() ? X86::RCX : X86::RDI; in expandCALL_RVMARKER() local
229 .addReg(TargetReg, RegState::Define) in expandCALL_RVMARKER()
|
| H A D | X86ISelLowering.cpp | 62113 Register TargetReg; in EmitKCFICheck() local
62122 TargetReg = Target.getReg(); in EmitKCFICheck()
62131 TargetReg = X86::R11; in EmitKCFICheck()
62139 .addReg(TargetReg) in EmitKCFICheck()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZAsmPrinter.cpp | 350 Register TargetReg = MI->getOperand(0).getReg(); in emitInstruction() local
361 if (TargetReg != ADAReg) { in emitInstruction()
362 IndexReg = TargetReg; in emitInstruction()
366 MCInstBuilder(SystemZ::LLILF).addReg(TargetReg).addImm(Disp)); in emitInstruction()
369 .addReg(TargetReg) in emitInstruction()
370 .addReg(TargetReg) in emitInstruction()
376 .addReg(TargetReg) in emitInstruction()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.h | 195 Register TargetReg) const;
|
| H A D | AArch64FrameLowering.cpp | 830 Register TargetReg = RealignmentPadding in allocateStackSpace() local
834 emitFrameOffset(MBB, MBBI, DL, TargetReg, AArch64::SP, -AllocSize, &TII, in allocateStackSpace()
841 .addReg(TargetReg, RegState::Kill) in allocateStackSpace()
920 Register TargetReg = findScratchNonCalleeSaveRegister(&MBB); in allocateStackSpace() local
921 assert(TargetReg != AArch64::NoRegister); in allocateStackSpace()
923 emitFrameOffset(MBB, MBBI, DL, TargetReg, AArch64::SP, -AllocSize, &TII, in allocateStackSpace()
928 BuildMI(MBB, MBBI, DL, TII.get(AArch64::ANDXri), TargetReg) in allocateStackSpace()
929 .addReg(TargetReg, RegState::Kill) in allocateStackSpace()
935 .addReg(TargetReg); in allocateStackSpace()
5551 Register TargetReg) const { in inlineStackProbeLoopExactMultiple()
[all …]
|
| H A D | AArch64InstrInfo.h | 559 Register TargetReg,
|
| H A D | AArch64InstrInfo.cpp | 10313 Register TargetReg, bool FrameSetup) const { in probedStackAlloc() argument
10314 assert(TargetReg != AArch64::SP && "New top of stack cannot already be in SP"); in probedStackAlloc()
10344 .addReg(TargetReg) in probedStackAlloc()
10369 .addReg(TargetReg) in probedStackAlloc()
|
| H A D | AArch64ISelLowering.cpp | 2850 Register TargetReg = MI.getOperand(0).getReg(); in EmitDynamicProbedAlloc() local
2852 TII.probedStackAlloc(MBBI, TargetReg, false); in EmitDynamicProbedAlloc()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVLegalizerInfo.cpp | 775 Register TargetReg; in legalizeBRJT() local
786 TargetReg = MIRBuilder.buildPtrAdd(PtrTy, PtrReg, Load).getReg(0); in legalizeBRJT()
792 TargetReg = MIRBuilder.buildIntToPtr(PtrTy, Load).getReg(0); in legalizeBRJT()
796 TargetReg = MIRBuilder.buildLoad(PtrTy, Addr, *MMO).getReg(0); in legalizeBRJT()
800 MIRBuilder.buildBrIndirect(TargetReg); in legalizeBRJT()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 866 Register TargetReg = I->getOperand(1).getReg(); in expandEhReturn() local
874 .addReg(TargetReg) in expandEhReturn()
877 .addReg(TargetReg) in expandEhReturn()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFrameLowering.cpp | 179 Register TargetReg) { in buildGitPtr() argument
184 Register TargetLo = TRI->getSubReg(TargetReg, AMDGPU::sub0); in buildGitPtr()
185 Register TargetHi = TRI->getSubReg(TargetReg, AMDGPU::sub1); in buildGitPtr()
190 .addReg(TargetReg, RegState::ImplicitDefine); in buildGitPtr()
193 BuildMI(MBB, I, DL, GetPC64, TargetReg); in buildGitPtr()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 3087 Register TargetReg = MI.getOperand(0).getReg(); in expandVSXMemPseudo() local
3089 if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) || in expandVSXMemPseudo()
3090 (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31)) in expandVSXMemPseudo()
3221 Register TargetReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
3222 if (PPC::VSFRCRegClass.contains(TargetReg)) { in expandPostRAPseudo()
3243 Register TargetReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
3244 if (PPC::VSFRCRegClass.contains(TargetReg)) in expandPostRAPseudo()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 472 const SmallSet<Register, 2> &TargetReg,
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3791 Register TargetReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in selectBrJT() local
3795 {TargetReg, ScratchReg}, {JTAddr, Index}) in selectBrJT()
3801 MIB.buildInstr(AArch64::BR, {}, {TargetReg}); in selectBrJT()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 3745 Register TargetReg, Register InsertReg, in buildBitFieldInsert() argument
3747 LLT TargetTy = B.getMRI()->getType(TargetReg); in buildBitFieldInsert()
3761 auto MaskedOldElt = B.buildAnd(TargetTy, TargetReg, InvShiftedMask); in buildBitFieldInsert()
|