Searched refs:TSEC_MIIMCFG_CLKDIV28 (Results 1 – 2 of 2) sorted by relevance
316 #define TSEC_MIIMCFG_CLKDIV28 0x00000007 /* source clock divided by 28 */ macro
429 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28); in tsec_init_locked()