| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | EarlyIfConversion.cpp | 113 unsigned TReg = 0, FReg = 0; member
521 PI.TReg = PI.PHI->getOperand(i).getReg(); in canConvertIf()
525 assert(Register::isVirtualRegister(PI.TReg) && "Bad PHI"); in canConvertIf()
530 PI.TReg, PI.FReg, PI.CondCycles, PI.TCycles, in canConvertIf()
566 const TargetInstrInfo *TII, Register TReg, in hasSameValue() argument
568 if (TReg == FReg) in hasSameValue()
571 if (!TReg.isVirtual() || !FReg.isVirtual()) in hasSameValue()
574 const MachineInstr *TDef = MRI.getUniqueVRegDef(TReg); in hasSameValue()
602 int TIdx = TDef->findRegisterDefOperandIdx(TReg, /*TRI=*/nullptr); in hasSameValue()
623 if (hasSameValue(*MRI, TII, PI.TReg, PI.FReg)) { in replacePHIInstrs()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 2566 Register TReg = MRI.createVirtualRegister(RC); in emitSjLjDispatchBlock() local
2572 BuildMI(DispContBB, DL, TII->get(VE::LDrri), TReg) in emitSjLjDispatchBlock()
2577 .addReg(TReg, getKillRegState(true)) in emitSjLjDispatchBlock()
2592 Register TReg = MRI.createVirtualRegister(RC); in emitSjLjDispatchBlock() local
2605 BuildMI(DispContBB, DL, TII->get(VE::ADDSLrr), TReg) in emitSjLjDispatchBlock()
2609 .addReg(TReg, getKillRegState(true)) in emitSjLjDispatchBlock()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMAsmPrinter.cpp | 1520 Register TReg = MI->getOperand(0).getReg(); in emitInstruction() local
1523 if (TIP.first == TReg) { in emitInstruction()
1531 ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym)); in emitInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 606 Register TReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass); in insertSelect() local
608 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg); in insertSelect()
610 TrueReg = TReg; in insertSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 4932 unsigned TReg = Inst.getOperand(2).getReg(); in expandRotation() local
4946 TOut.emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandRotation()
4952 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4977 TOut.emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandRotation()
4979 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
5057 unsigned TReg = Inst.getOperand(2).getReg(); in expandDRotation() local
5071 TOut.emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandDRotation()
5077 TOut.emitRRR(Mips::DROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandDRotation()
5102 TOut.emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandDRotation()
5104 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandDRotation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 5251 SDValue TReg = getI8Imm(TIndex, dl); in Select() local
5260 SDValue Ops[] = { Base, Scale, Index, Disp, Segment, TReg, Chain }; in Select()
5263 SDValue Ops[] = { TReg, Base, Scale, Index, Disp, Segment, Chain }; in Select()
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| H A D | X86ISelLowering.cpp | 36404 Register TReg = MRI->createVirtualRegister(&X86::GR64RegClass); in EmitSjLjDispatchBlock() local
36417 BuildMI(DispContBB, MIMD, TII->get(X86::ADD64rr), TReg) in EmitSjLjDispatchBlock()
36421 BuildMI(DispContBB, MIMD, TII->get(X86::JMP64r)).addReg(TReg); in EmitSjLjDispatchBlock()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3415 const Register TReg = Sel.getTrueReg(); in select() local
3427 if (!emitSelect(Sel.getReg(0), TReg, FReg, AArch64CC::NE, MIB)) in select()
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