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Searched refs:TRI (Results 1 – 25 of 585) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineCopyPropagation.cpp129 const TargetRegisterInfo &TRI) { in getPreservedRegUnits() argument
137 PreservedRegUnits.resize(TRI.getNumRegUnits()); in getPreservedRegUnits()
138 for (unsigned SafeReg = 0, E = TRI.getNumRegs(); SafeReg < E; ++SafeReg) in getPreservedRegUnits()
140 for (auto SafeUnit : TRI.regunits(SafeReg)) in getPreservedRegUnits()
150 const TargetRegisterInfo &TRI) { in markRegsUnavailable() argument
153 for (MCRegUnit Unit : TRI.regunits(Reg)) { in markRegsUnavailable()
162 void invalidateRegister(MCRegister Reg, const TargetRegisterInfo &TRI, in invalidateRegister() argument
174 auto Dest = TRI.regunits(CopyOperands->Destination->getReg().asMCReg()); in invalidateRegister()
175 auto Src = TRI.regunits(CopyOperands->Source->getReg().asMCReg()); in invalidateRegister()
180 for (MCRegUnit Unit : TRI.regunits(Reg)) { in invalidateRegister()
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H A DRegisterBank.cpp24 const TargetRegisterInfo &TRI) const {
25 for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) { in RegisterBank()
26 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in RegisterBank()
37 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
44 assert(RBI.getMaximumSize(getID()) >= TRI.getRegSizeInBits(SubRC) && in verify()
66 LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const { in covers()
67 print(dbgs(), /* IsForDebug */ true, TRI);
72 const TargetRegisterInfo *TRI) const { in isValid()
85 if (!TRI || NumRegClasses == 0) in dump()
87 assert(NumRegClasses == TRI in dump()
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H A DFixupStatepointCallerSaved.cpp97 static unsigned getRegisterSize(const TargetRegisterInfo &TRI, Register Reg) { in getRegisterSize() argument
98 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); in getRegisterSize()
99 return TRI.getSpillSize(*RC); in getRegisterSize()
118 const TargetRegisterInfo &TRI) { in performCopyPropagation() argument
120 int Idx = RI->findRegisterUseOperandIdx(Reg, &TRI, false); in performCopyPropagation()
133 if (It->readsRegister(Reg, &TRI) && !Use) in performCopyPropagation()
135 if (It->modifiesRegister(Reg, &TRI)) { in performCopyPropagation()
150 if (getRegisterSize(TRI, Reg) != getRegisterSize(TRI, SrcReg)) in performCopyPropagation()
154 << printReg(Reg, &TRI) << " -> " << printReg(SrcReg, &TRI) in performCopyPropagation()
209 const TargetRegisterInfo &TRI; member in __anon2f435cf10211::FrameIndexesCache
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H A DRegisterClassInfo.cpp50 if (STI.getRegisterInfo() != TRI || Reverse != Rev) { in runOnMachineFunction()
52 TRI = STI.getRegisterInfo(); in runOnMachineFunction()
53 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
85 CalleeSavedAliases.assign(TRI->getNumRegUnits(), 0); in runOnMachineFunction()
87 for (MCRegUnit U : TRI->regunits(*I)) in runOnMachineFunction()
97 BitVector CSRHintsForAllocOrder(TRI->getNumRegs()); in runOnMachineFunction()
99 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) in runOnMachineFunction()
107 RegCosts = TRI->getRegisterCosts(*MF); in runOnMachineFunction()
118 unsigned NumPSets = TRI->getNumRegPressureSets(); in runOnMachineFunction()
189 TRI->getLargestLegalSuperClass(RC, *MF)) in compute()
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H A DLiveRegMatrix.cpp62 TRI = MF.getSubtarget().getRegisterInfo(); in init()
66 unsigned NumRegUnits = TRI->getNumRegUnits(); in init()
87 static bool foreachUnit(const TargetRegisterInfo *TRI, in foreachUnit() argument
91 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
103 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in foreachUnit()
112 LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg(), TRI) << " to " in assign()
113 << printReg(PhysReg, TRI) << ':'); in assign()
118 TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) { in assign()
119 LLVM_DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << ' ' << Range); in assign()
130 LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg(), TRI) in unassign()
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H A DAggressiveAntiDepBreaker.cpp123 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI) { in AggressiveAntiDepBreaker()
127 BitVector CPSet = TRI->getAllocatableSet(MF, RC); in AggressiveAntiDepBreaker()
137 << " " << printReg(r, TRI)); in AggressiveAntiDepBreaker()
147 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB); in StartBlock()
156 for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) { in StartBlock()
174 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { in StartBlock()
202 for (unsigned Reg = 1; Reg != TRI->getNumRegs(); ++Reg) { in Observe()
211 << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg) in Observe()
248 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) in GetPassthruRegs()
303 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) in HandleLastUse()
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H A DRDFRegisters.cpp30 : TRI(tri) { in PhysicalRegisterInfo()
31 RegInfos.resize(TRI.getNumRegs()); in PhysicalRegisterInfo()
33 BitVector BadRC(TRI.getNumRegs()); in PhysicalRegisterInfo()
34 for (const TargetRegisterClass *RC : TRI.regclasses()) { in PhysicalRegisterInfo()
47 UnitInfos.resize(TRI.getNumRegUnits()); in PhysicalRegisterInfo()
49 for (uint32_t U = 0, NU = TRI.getNumRegUnits(); U != NU; ++U) { in PhysicalRegisterInfo()
52 MCRegUnitRootIterator R(U, &TRI); in PhysicalRegisterInfo()
60 for (MCRegUnitMaskIterator I(F, &TRI); I.isValid(); ++I) { in PhysicalRegisterInfo()
69 for (const uint32_t *RM : TRI.getRegMasks()) in PhysicalRegisterInfo()
79 BitVector PU(TRI.getNumRegUnits()); in PhysicalRegisterInfo()
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H A DTargetRegisterInfo.cpp107 Printable printReg(Register Reg, const TargetRegisterInfo *TRI, in printReg() argument
109 return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) { in printReg()
121 } else if (!TRI) in printReg()
123 else if (Reg < TRI->getNumRegs()) { in printReg()
125 printLowerCase(TRI->getName(Reg), OS); in printReg()
130 if (TRI) in printReg()
131 OS << ':' << TRI->getSubRegIndexName(SubIdx); in printReg()
138 Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) { in printRegUnit() argument
139 return Printable([Unit, TRI](raw_ostream &OS) { in printRegUnit()
141 if (!TRI) { in printRegUnit()
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H A DDetectDeadLanes.cpp42 const TargetRegisterInfo *TRI) in DeadLaneDetector() argument
43 : MRI(MRI), TRI(TRI) { in DeadLaneDetector()
79 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); in isCrossCopy() local
93 SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx); in isCrossCopy()
99 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA, in isCrossCopy()
102 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx); in isCrossCopy()
104 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx); in isCrossCopy()
105 return !TRI.getCommonSubClass(SrcRC, DstRC); in isCrossCopy()
118 UsedLanes = TRI->composeSubRegIndexLaneMask(MOSubReg, UsedLanes); in addUsedLanesOnOperand()
159 return TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
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H A DCriticalAntiDepBreaker.cpp44 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), in CriticalAntiDepBreaker()
45 Classes(TRI->getNumRegs(), nullptr), KillIndices(TRI->getNumRegs(), 0), in CriticalAntiDepBreaker()
46 DefIndices(TRI->getNumRegs(), 0), KeepRegs(TRI->getNumRegs(), false) {} in CriticalAntiDepBreaker()
52 for (unsigned i = 1, e = TRI->getNumRegs(); i != e; ++i) { in StartBlock()
69 for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) { in StartBlock()
87 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) { in StartBlock()
114 for (unsigned Reg = 1; Reg != TRI->getNumRegs(); ++Reg) { in Observe()
190 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); in PrescanInstruction()
200 for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) { in PrescanInstruction()
217 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) in PrescanInstruction()
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H A DRegisterScavenging.cpp57 TRI = MF.getSubtarget().getRegisterInfo(); in init()
59 LiveUnits.init(*TRI); in init()
103 LLVM_DEBUG(dbgs() << "Scavenger found unused reg: " << printReg(Reg, TRI) in FindUnusedReg()
112 BitVector Mask(TRI->getNumRegs()); in getRegsAvailable()
137 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); in findSurvivorBackwards() local
138 LiveRegUnits Used(TRI); in findSurvivorBackwards()
229 unsigned NeedSize = TRI->getSpillSize(RC); in spill()
230 Align NeedAlign = TRI->getSpillAlign(RC); in spill()
269 if (!TRI->saveScavengerRegister(*MBB, Before, UseMI, &RC, Reg)) { in spill()
274 TRI->getName(Reg) + " from class " + in spill()
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H A DRegAllocFast.cpp188 const TargetRegisterInfo *TRI = nullptr; member in __anon43a0a7eb0111::RegAllocFastImpl
283 for (MCRegUnit Unit : TRI->regunits(PhysReg)) in markRegUsedInInstr()
298 for (MCRegUnit Unit : TRI->regunits(PhysReg)) in isRegUsedInInstr()
307 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in markPhysRegUsedInInstr()
315 for (MCRegUnit Unit : TRI->regunits(PhysReg)) in unmarkRegUsedInInstr()
448 return ShouldAllocateRegisterImpl(*TRI, *MRI, Reg); in shouldAllocateRegister()
452 for (MCRegUnit Unit : TRI->regunits(PhysReg)) in setPhysRegState()
457 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in isPhysRegFree()
475 unsigned Size = TRI->getSpillSize(RC); in getStackSpaceFor()
476 Align Alignment = TRI->getSpillAlign(RC); in getStackSpaceFor()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRewritePartialRegUses.cpp50 const SIRegisterInfo *TRI; member in __anonf1e524d80111::GCNRewritePartialRegUsesImpl
156 for (unsigned Idx = 1, E = TRI->getNumSubRegIndices(); Idx < E; ++Idx) { in getSubReg()
157 if (TRI->getSubRegIdxOffset(Idx) == Offset && in getSubReg()
158 TRI->getSubRegIdxSize(Idx) == Size) { in getSubReg()
169 unsigned Offset = TRI->getSubRegIdxOffset(SubReg) - RShift; in shiftSubReg()
170 return getSubReg(Offset, TRI->getSubRegIdxSize(SubReg)); in shiftSubReg()
178 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) { in getSuperRegClassMask()
195 BV.resize(TRI->getNumRegClasses()); in getAllocatableAndAlignedRegClassMask()
196 for (unsigned ClassID = 0; ClassID < TRI->getNumRegClasses(); ++ClassID) { in getAllocatableAndAlignedRegClassMask()
197 auto *RC = TRI->getRegClass(ClassID); in getAllocatableAndAlignedRegClassMask()
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H A DSIFrameLowering.cpp80 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in getVGPRSpillLaneOrTempRegister() local
81 unsigned Size = TRI->getSpillSize(RC); in getVGPRSpillLaneOrTempRegister()
82 Align Alignment = TRI->getSpillAlign(RC); in getVGPRSpillLaneOrTempRegister()
97 if (TRI->spillSGPRToVGPR() && in getVGPRSpillLaneOrTempRegister()
107 dbgs() << printReg(SGPR, TRI) << " requires fallback spill to " in getVGPRSpillLaneOrTempRegister()
108 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane in getVGPRSpillLaneOrTempRegister()
119 << printReg(SGPR, TRI) << '\n'); in getVGPRSpillLaneOrTempRegister()
126 LLVM_DEBUG(dbgs() << "Saving " << printReg(SGPR, TRI) << " with copy to " in getVGPRSpillLaneOrTempRegister()
127 << printReg(ScratchSGPR, TRI) << '\n'); in getVGPRSpillLaneOrTempRegister()
134 static void buildPrologSpill(const GCNSubtarget &ST, const SIRegisterInfo &TRI, in buildPrologSpill() argument
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H A DSIFixSGPRCopies.cpp134 const SIRegisterInfo *TRI; member in __anon8637e2150111::SIFixSGPRCopies
204 const SIRegisterInfo &TRI, in getCopyRegClasses() argument
211 : TRI.getPhysRegBaseClass(SrcReg); in getCopyRegClasses()
218 : TRI.getPhysRegBaseClass(DstReg); in getCopyRegClasses()
225 const SIRegisterInfo &TRI) { in isVGPRToSGPRCopy() argument
226 return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) && in isVGPRToSGPRCopy()
227 TRI.hasVectorRegisters(SrcRC); in isVGPRToSGPRCopy()
232 const SIRegisterInfo &TRI) { in isSGPRToVGPRCopy() argument
233 return DstRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(SrcRC) && in isSGPRToVGPRCopy()
234 TRI.hasVectorRegisters(DstRC); in isSGPRToVGPRCopy()
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H A DSIMachineFunctionInfo.cpp197 const SIRegisterInfo &TRI) { in addPrivateSegmentBuffer() argument
199 ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addPrivateSegmentBuffer()
205 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) { in addDispatchPtr() argument
206 ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchPtr()
212 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) { in addQueuePtr() argument
213 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addQueuePtr()
219 Register SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) { in addKernargSegmentPtr() argument
221 = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addKernargSegmentPtr()
227 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) { in addDispatchID() argument
228 ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchID()
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H A DSILowerSGPRSpills.cpp43 const SIRegisterInfo *TRI = nullptr; member in __anoneec5f4eb0111::SILowerSGPRSpills
103 const TargetRegisterInfo *TRI) { in isLiveIntoMBB() argument
104 for (MCRegAliasIterator R(Reg, TRI, true); R.isValid(); ++R) { in isLiveIntoMBB()
119 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); in insertCSRSaves() local
124 if (!TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, TRI)) { in insertCSRSaves()
130 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass( in insertCSRSaves()
137 const bool IsLiveIn = isLiveIntoMBB(Reg, SaveBlock, TRI); in insertCSRSaves()
139 RC, TRI, Register()); in insertCSRSaves()
168 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); in insertCSRRestores() local
176 if (!TFI->restoreCalleeSavedRegisters(RestoreBlock, I, CSI, TRI)) { in insertCSRRestores()
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H A DR600ExpandSpecialInstrs.cpp77 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction() local
125 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction() local
128 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; in runOnMachineFunction()
131 bool Mask = (Chan != TRI.getHWRegChan(DstReg)); in runOnMachineFunction()
155 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 && in runOnMachineFunction()
156 (TRI.getEncodingValue(Src1) & 0xff) < 127) in runOnMachineFunction()
157 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1)); in runOnMachineFunction()
212 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
213 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
218 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLivePhysRegs.h53 const TargetRegisterInfo *TRI = nullptr; variable
62 LivePhysRegs(const TargetRegisterInfo &TRI) : TRI(&TRI) { in LivePhysRegs() argument
63 LiveRegs.setUniverse(TRI.getNumRegs()); in LivePhysRegs()
70 void init(const TargetRegisterInfo &TRI) { in init() argument
71 this->TRI = &TRI; in init()
73 LiveRegs.setUniverse(TRI.getNumRegs()); in init()
84 assert(TRI && "LivePhysRegs is not initialized."); in addReg()
85 assert(Reg < TRI->getNumRegs() && "Expected a physical register."); in addReg()
86 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) in addReg()
93 assert(TRI && "LivePhysRegs is not initialized."); in removeReg()
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H A DLiveRegUnits.h32 const TargetRegisterInfo *TRI = nullptr; variable
40 LiveRegUnits(const TargetRegisterInfo &TRI) { in LiveRegUnits() argument
41 init(TRI); in LiveRegUnits()
51 const TargetRegisterInfo *TRI) { in accumulateUsedDefed() argument
64 if (!TRI->isConstantPhysReg(Reg)) in accumulateUsedDefed()
74 void init(const TargetRegisterInfo &TRI) { in init() argument
75 this->TRI = &TRI; in init()
77 Units.resize(TRI.getNumRegUnits()); in init()
88 for (MCRegUnit Unit : TRI->regunits(Reg)) in addReg()
95 for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) { in addRegMasked()
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H A DCFIInstBuilder.h34 const TargetRegisterInfo &TRI; variable
42 TRI(*MF.getSubtarget().getRegisterInfo()),
62 nullptr, TRI.getDwarfRegNum(Reg, IsEH), Offset)); in buildDefCFA()
67 nullptr, TRI.getDwarfRegNum(Reg, IsEH))); in buildDefCFARegister()
80 nullptr, TRI.getDwarfRegNum(Reg, IsEH), Offset)); in buildOffset()
93 nullptr, TRI.getDwarfRegNum(Reg1, IsEH), in buildRegister()
94 TRI.getDwarfRegNum(Reg2, IsEH))); in buildRegister()
103 nullptr, TRI.getDwarfRegNum(Reg, IsEH))); in buildRestore()
108 nullptr, TRI.getDwarfRegNum(Reg, IsEH))); in buildUndefined()
113 nullptr, TRI.getDwarfRegNum(Reg, IsEH))); in buildSameValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsOptionRecord.h46 const MCRegisterInfo *TRI = Context.getRegisterInfo(); in MipsRegInfoRecord() local
47 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
48 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()
49 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID)); in MipsRegInfoRecord()
50 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); in MipsRegInfoRecord()
51 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); in MipsRegInfoRecord()
52 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID)); in MipsRegInfoRecord()
53 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID)); in MipsRegInfoRecord()
54 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID)); in MipsRegInfoRecord()
55 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID)); in MipsRegInfoRecord()
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreMachineFunctionInfo.cpp46 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); in createLRSpillSlot() local
50 LRSpillSlot = MFI.CreateFixedObject(TRI.getSpillSize(RC), 0, true); in createLRSpillSlot()
52 LRSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), in createLRSpillSlot()
53 TRI.getSpillAlign(RC), true); in createLRSpillSlot()
64 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); in createFPSpillSlot() local
67 MFI.CreateStackObject(TRI.getSpillSize(RC), TRI.getSpillAlign(RC), true); in createFPSpillSlot()
77 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); in createEHSpillSlot() local
79 unsigned Size = TRI.getSpillSize(RC); in createEHSpillSlot()
80 Align Alignment = TRI.getSpillAlign(RC); in createEHSpillSlot()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp71 const PPCRegisterInfo &TRI; member in __anone05d911e0111::PPCInstructionSelector
92 : TM(TM), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), in PPCInstructionSelector()
131 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, in selectCopy() argument
138 const RegisterBank *DstRegBank = RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
208 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); in selectIntToFP()
238 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); in selectFPToInt()
245 const RegisterBank *DstRegBank = RBI.getRegBank(DstReg, MRI, TRI); in selectZExt()
272 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); in selectZExt()
307 .constrainAllUses(TII, TRI, RBI); in selectI64ImmDirect()
313 .constrainAllUses(TII, TRI, RBI); in selectI64ImmDirect()
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kFrameLowering.cpp40 TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) { in M68kFrameLowering()
42 StackPtr = TRI->getStackRegister(); in M68kFrameLowering()
47 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); in hasFPImpl() local
51 TRI->hasStackRealignment(MF); in hasFPImpl()
63 (hasFP(MF) && !TRI->hasStackRealignment(MF)) || in canSimplifyCallFramePseudos()
64 TRI->hasBasePointer(MF); in canSimplifyCallFramePseudos()
85 if (TRI->hasBasePointer(MF)) in getFrameIndexReference()
86 FrameReg = TRI->getBaseRegister(); in getFrameIndexReference()
87 else if (TRI->hasStackRealignment(MF)) in getFrameIndexReference()
88 FrameReg = TRI->getStackRegister(); in getFrameIndexReference()
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