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Searched refs:TRC (Results 1 – 25 of 36) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp74 unsigned Lane, const TargetRegisterClass *TRC);
97 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
133 const TargetRegisterClass *TRC) { in usesRegClass() argument
139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
141 return TRC->contains(Reg); in usesRegClass()
270 const TargetRegisterClass *TRC = in optimizeSDPattern() local
272 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
433 const TargetRegisterClass *TRC) { in createExtractSubreg() argument
434 Register Out = MRI->createVirtualRegister(TRC); in createExtractSubreg()
H A DARMLoadStoreOptimizer.cpp2427 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); in RescheduleOps() local
2428 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps()
2429 MRI->constrainRegClass(SecondReg, TRC); in RescheduleOps()
3017 const TargetRegisterClass *TRC = TII->getRegClass(MCID, BaseOp, TRI, *MF); in AdjustBaseAndOffset() local
3018 MRI.constrainRegClass(NewBaseReg, TRC); in AdjustBaseAndOffset()
3074 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); in createPostIncLoadStore() local
3075 MRI.constrainRegClass(NewReg, TRC); in createPostIncLoadStore()
3077 TRC = TII->getRegClass(MCID, 2, TRI, *MF); in createPostIncLoadStore()
3078 MRI.constrainRegClass(MI->getOperand(1).getReg(), TRC); in createPostIncLoadStore()
H A DARMISelLowering.cpp10884 const TargetRegisterClass *TRC = isThumb ? &ARM::tGPRRegClass in SetupEntryBlockForSjLj() local
10903 Register NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10909 Register NewVReg2 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10915 Register NewVReg3 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10933 Register NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10938 Register NewVReg2 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10943 Register NewVReg3 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10948 Register NewVReg4 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10954 Register NewVReg5 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10969 Register NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kRegisterInfo.cpp107 const TargetRegisterClass &TRC) const { in getRegisterOrder()
108 for (unsigned i = 0; i < TRC.getNumRegs(); ++i) { in getRegisterOrder()
109 if (regsOverlap(Reg, TRC.getRegister(i))) { in getRegisterOrder()
H A DM68kRegisterInfo.h77 int getRegisterOrder(unsigned Reg, const TargetRegisterClass &TRC) const;
/freebsd/usr.sbin/lpr/lpd/
H A Dprintjob.c1496 #define TRC(q) (((q)-' ')&0177) macro
1510 d = dropit(c = TRC(cc = *sp++)); in scan_out()
1535 case TRC('_'): in dropit()
1536 case TRC(';'): in dropit()
1537 case TRC(','): in dropit()
1538 case TRC('g'): in dropit()
1539 case TRC('j'): in dropit()
1540 case TRC('p'): in dropit()
1541 case TRC('q'): in dropit()
1542 case TRC('y'): in dropit()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp522 const TargetRegisterClass *TRC = in EmitSubregNode() local
541 TRC == MRI->getRegClass(SrcReg)) { in EmitSubregNode()
547 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode()
561 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode()
678 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); in EmitRegSequence() local
680 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); in EmitRegSequence()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp515 const TargetRegisterClass &TRC = *getRegClass(Reg); in getMaxLaneMaskForVReg() local
516 return TRC.getLaneMask(); in getMaxLaneMaskForVReg()
H A DLiveDebugVariables.cpp1588 const TargetRegisterClass *TRC = MRI.getRegClass(VirtReg); in rewriteLocations() local
1589 bool Success = TII.getStackSlotRange(TRC, Loc.getSubReg(), SpillSize, in rewriteLocations()
1900 const TargetRegisterClass *TRC = MRI.getRegClass(Reg); in emitDebugValues() local
1903 unsigned regSizeInBits = TRI->getRegSizeInBits(*TRC); in emitDebugValues()
1911 TII->getStackSlotRange(TRC, SubReg, SpillSize, SpillOffset, *MF); in emitDebugValues()
H A DRegAllocPBQP.cpp614 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); in initializeGraph() local
622 ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF); in initializeGraph()
H A DMachineSink.cpp1801 const TargetRegisterClass *TRC = MRI->getRegClass(DefMO.getReg()); in aggressivelySinkIntoCycle() local
1802 Register DestReg = MRI->createVirtualRegister(TRC); in aggressivelySinkIntoCycle()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyAsmPrinter.cpp66 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo); in getRegType() local
69 if (TRI->isTypeLegalForClass(*TRC, T)) in getRegType()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp556 const auto *TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI, in getRegSizeInBytes() local
558 return TRI->getRegSizeInBits(*TRC) / 8; in getRegSizeInBytes()
/freebsd/contrib/llvm-project/clang/include/clang/AST/
H A DASTNodeTraverser.h559 if (const AssociatedConstraint &TRC = D->getTrailingRequiresClause()) in VisitFunctionDecl() local
560 Visit(TRC.ConstraintExpr); in VisitFunctionDecl()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h1515 const TargetRegisterClass &TRC, in isOfRegClass() argument
1519 return RC == &TRC; in isOfRegClass()
1521 return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg); in isOfRegClass()
/freebsd/contrib/llvm-project/clang/include/clang/Sema/
H A DDeclSpec.h2629 void setTrailingRequiresClause(Expr *TRC) { in setTrailingRequiresClause() argument
2630 TrailingRequiresClause = TRC; in setTrailingRequiresClause()
2632 SetRangeEnd(TRC->getEndLoc()); in setTrailingRequiresClause()
/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaTemplateVariadic.cpp1115 if (Expr *TRC = D.getTrailingRequiresClause()) in containsUnexpandedParameterPacks() local
1116 if (TRC->containsUnexpandedParameterPack()) in containsUnexpandedParameterPacks()
H A DSemaLambda.cpp1545 if (const AssociatedConstraint &TRC = Method->getTrailingRequiresClause()) { in ActOnStartOfLambdaDefinition() local
1568 Diag(TRC.ConstraintExpr->getBeginLoc(), in ActOnStartOfLambdaDefinition()
/freebsd/sys/arm64/vmm/
H A Dvmm_reset.c256 TRC, TRAP); in reset_vm_el2_regs()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp4729 const TargetRegisterClass *TRC = ::getRegClass(MI, Reg); in isHForm() local
4730 return TRC == &AArch64::FPR16RegClass || in isHForm()
4731 TRC == &AArch64::FPR16_loRegClass; in isHForm()
4743 const TargetRegisterClass *TRC = ::getRegClass(MI, Reg); in isQForm() local
4744 return TRC == &AArch64::FPR128RegClass || in isQForm()
4745 TRC == &AArch64::FPR128_loRegClass; in isQForm()
4795 const TargetRegisterClass *TRC = ::getRegClass(MI, Reg); in isFpOrNEON() local
4796 return TRC == &AArch64::FPR128RegClass || in isFpOrNEON()
4797 TRC == &AArch64::FPR128_loRegClass || in isFpOrNEON()
4798 TRC == &AArch64::FPR64RegClass || in isFpOrNEON()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h85 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {} in DstOp() argument
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/LiveDebugValues/
H A DInstrRefBasedImpl.cpp1595 const TargetRegisterClass *TRC = nullptr; in getValueForInstrRef() local
1598 TRC = TRCI; in getValueForInstrRef()
1599 assert(TRC && "Couldn't find target register class?"); in getValueForInstrRef()
1603 unsigned MainRegSize = TRI->getRegSizeInBits(*TRC); in getValueForInstrRef()
/freebsd/contrib/llvm-project/clang/lib/AST/
H A DDeclTemplate.cpp293 if (const AssociatedConstraint &TRC = FD->getTrailingRequiresClause()) in getAssociatedConstraints() local
294 ACs.emplace_back(TRC); in getAssociatedConstraints()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp2106 const TargetRegisterClass *TRC; in createVR() local
2108 TRC = &Hexagon::PredRegsRegClass; in createVR()
2110 TRC = &Hexagon::IntRegsRegClass; in createVR()
2112 TRC = &Hexagon::DoubleRegsRegClass; in createVR()
2117 Register NewReg = MRI.createVirtualRegister(TRC); in createVR()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp1173 const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8 in simplifyCode() local
1176 MRI->setRegClass(DominatorReg, TRC); in simplifyCode()

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