| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 37 TIED_TO = 0, // Must be allocated the same register as specified value. enumerator
43 ((1 << MCOI::TIED_TO) | ((op) << (4 + MCOI::TIED_TO * 4)))
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86BaseInfo.h | 978 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) in getOperandBias()
982 if (NumOps == 8 && Desc.getOperandConstraint(6, MCOI::TIED_TO) == 0) in getOperandBias()
987 if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && in getOperandBias()
988 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1) in getOperandBias()
992 if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && in getOperandBias()
993 (Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1 || in getOperandBias()
994 Desc.getOperandConstraint(8, MCOI::TIED_TO) == 1)) in getOperandBias()
|
| H A D | X86InstComments.cpp | 292 if (Desc.getOperandConstraint(MaskOp, MCOI::TIED_TO) != -1) in printMasking()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZHazardRecognizer.cpp | 127 MID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in has4RegOps()
|
| H A D | SystemZShortenInst.cpp | 66 if (MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) == 0 && in tieOpsIfNeeded()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVBaseInfo.h | 265 Desc.getOperandConstraint(Desc.getNumDefs(), MCOI::TIED_TO) == 0; in isFirstDefTiedToFirstUse()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGSDNodes.cpp | 218 if (MCID.getOperandConstraint(I, MCOI::TIED_TO) != -1) in ClusterNeighboringLoads()
456 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in AddSchedEdges()
|
| H A D | ScheduleDAGFast.cpp | 246 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in CopyAndMoveSuccessors()
|
| H A D | ScheduleDAGRRList.cpp | 1033 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in TryUnfoldSU()
2842 if (MCID.getOperandConstraint(i+NumRes, MCOI::TIED_TO) != -1) { in canClobber()
3082 if (MCID.getOperandConstraint(j+NumRes, MCOI::TIED_TO) == -1) in AddPseudoTwoAddrDeps()
|
| H A D | InstrEmitter.cpp | 385 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1; in AddRegisterOperand()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVAsmPrinter.cpp | 1106 assert(MCID.getOperandConstraint(OpNo, MCOI::TIED_TO) == 0 && in lowerRISCVVMachineInstrToMCInst()
1111 if (OutMCID.getOperandConstraint(OutMI.getNumOperands(), MCOI::TIED_TO) < in lowerRISCVVMachineInstrToMCInst()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 884 MCOI::OperandConstraint::TIED_TO); in getInstruction()
1099 OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) { in isMacDPP()
1103 MCOI::OperandConstraint::TIED_TO) == DST_IDX); in isMacDPP()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.cpp | 801 assert(OpDesc.getOperandConstraint(Component::SRC0, MCOI::TIED_TO) == -1); in ComponentProps()
802 assert(OpDesc.getOperandConstraint(Component::SRC1, MCOI::TIED_TO) == -1); in ComponentProps()
803 auto TiedIdx = OpDesc.getOperandConstraint(Component::SRC2, MCOI::TIED_TO); in ComponentProps()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 238 MI.getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) { in commuteInstructionImpl()
243 MI.getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) { in commuteInstructionImpl()
|
| H A D | MachineInstr.cpp | 282 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); in addOperand()
1700 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO); in hasComplexRegisterTies()
|
| H A D | MachineVerifier.cpp | 2549 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO); in visitMachineOperand()
2606 if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO)) in visitMachineOperand()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 9007 MCOI::OperandConstraint::TIED_TO) == -1; in isRegOrImmWithInputMods()
9783 Desc.getOperandConstraint(OldIdx, MCOI::TIED_TO) == -1; in cvtVOP3DPP()
9823 MCOI::TIED_TO); in cvtVOP3DPP()
9895 MCOI::TIED_TO); in cvtDPP()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 193 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO); in constrainSelectedInstRegOperands()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 3079 MCOI::TIED_TO) != -1)) { in findCommutedOpIndices()
7412 bool Tied1 = 0 == MI.getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO); in commuteOperandsForFold()
7413 bool Tied2 = 0 == MI.getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO); in commuteOperandsForFold()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 3801 int TiedOp = MCID.getOperandConstraint(1, MCOI::TIED_TO); in validateInstruction()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | Target.td | 731 /// - MC/MCInstrDesc.h:OperandConstraint::{TIED_TO, EARLY_CLOBBER}.
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1168 assert(MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) == 0 && in commuteInstructionImpl()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1020 int TiedOp = MCID.getOperandConstraint(VCCPos + 3, MCOI::TIED_TO); in AddThumbPredicate()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 5426 (MCID.getOperandConstraint(i, MCOI::TIED_TO) == -1) && in validateInstruction()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2557 int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO); in addVPTPredROperands()
|