Searched refs:TEGRA210_CLK_PLL_P (Results 1 – 4 of 4) sorted by relevance
274 #define TEGRA210_CLK_PLL_P 243 macro
500 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,501 <&tegra_car TEGRA210_CLK_PLL_P>,502 <&tegra_car TEGRA210_CLK_PLL_P>;
163 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,164 <&tegra_car TEGRA210_CLK_PLL_P>,165 <&tegra_car TEGRA210_CLK_PLL_P>;1387 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>;
358 PLL(TEGRA210_CLK_PLL_P, "pllP_out0", "osc_div_clk"),