Searched refs:TEGRA210_CLK_PLL_A_OUT0 (Results 1 – 2 of 2) sorted by relevance
1512 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;1525 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;1538 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;1551 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;1564 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;1632 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;1644 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;1656 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;2020 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;2024 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>,[all …]
280 #define TEGRA210_CLK_PLL_A_OUT0 249 macro