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Searched refs:TEGRA20_CLK_PLL_A_OUT0 (Results 1 – 13 of 13) sorted by relevance

/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dtegra20-car.h136 #define TEGRA20_CLK_PLL_A_OUT0 113 macro
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra20-plutux.dts58 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
H A Dtegra20-tec.dts67 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
H A Dtegra20-medcom-wide.dts93 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
H A Dtegra20-trimslice.dts493 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
H A Dtegra20-ventana.dts720 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
H A Dtegra20-paz00.dts730 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
H A Dtegra20-harmony.dts759 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
H A Dtegra20-colibri.dtsi774 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
H A Dtegra20-seaboard.dts918 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
H A Dtegra20.dtsi404 assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_A_OUT0>;
H A Dtegra20-asus-tf101.dts1203 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
H A Dtegra20-acer-a500-picasso.dts1435 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,