| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 606 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
609 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
617 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size())); in FindSuitableFreeRegisters()
619 unsigned OrigR = RenameOrder[SuperRC]; in FindSuitableFreeRegisters()
712 RenameOrder.erase(SuperRC); in FindSuitableFreeRegisters()
713 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R)); in FindSuitableFreeRegisters()
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| H A D | RegAllocGreedy.cpp | 1337 const MachineInstr *MI, Register Reg, const TargetRegisterClass *SuperRC, in getNumAllocatableRegsForConstraints() argument
1340 assert(SuperRC && "Invalid register class"); in getNumAllocatableRegsForConstraints()
1343 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI, in getNumAllocatableRegsForConstraints()
1439 const TargetRegisterClass *SuperRC = in tryInstructionSplit() local
1442 RegClassInfo.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
1452 getNumAllocatableRegsForConstraints(MI, VirtReg.reg(), SuperRC, in tryInstructionSplit()
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| H A D | TargetLoweringBase.cpp | 1238 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); in findRepresentativeClass() local
1240 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC)) in findRepresentativeClass()
1242 if (!isLegalRC(*TRI, *SuperRC)) in findRepresentativeClass()
1244 BestRC = SuperRC; in findRepresentativeClass()
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| H A D | MachineVerifier.cpp | 2628 const TargetRegisterClass *SuperRC = in visitMachineOperand() local
2630 if (!SuperRC) { in visitMachineOperand()
2634 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 1260 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in copyFromSrcRegs() local
1261 Register SrcReg = MRI->createVirtualRegister(SuperRC); in copyFromSrcRegs()
1308 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeRead2Pair() local
1309 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeRead2Pair()
1437 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeImagePair() local
1439 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeImagePair()
1473 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeSMemLoadImmPair() local
1475 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeSMemLoadImmPair()
1506 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeBufferLoadPair() local
1509 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeBufferLoadPair()
[all …]
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| H A D | SIRegisterInfo.h | 261 /// Returns a register class which is compatible with \p SuperRC, such that a
266 getCompatibleSubRegClass(const TargetRegisterClass *SuperRC,
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| H A D | SIInstrInfo.h | 110 const TargetRegisterClass *SuperRC,
115 const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC,
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| H A D | SIRegisterInfo.cpp | 2907 SIRegisterInfo::getCompatibleSubRegClass(const TargetRegisterClass *SuperRC, in getCompatibleSubRegClass() argument
2912 getMatchingSuperRegClass(SuperRC, SubRC, SubIdx); in getCompatibleSubRegClass()
2913 return MatchRC && MatchRC->hasSubClassEq(SuperRC) ? MatchRC : nullptr; in getCompatibleSubRegClass()
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| H A D | SIInstrInfo.cpp | 5653 const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, in buildExtractSubReg() argument
5667 const MachineOperand &Op, const TargetRegisterClass *SuperRC, in buildExtractSubRegOrImm() argument
5678 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC, in buildExtractSubRegOrImm()
5707 const TargetRegisterClass *SuperRC = RI.getLargestLegalSuperClass(RC, *MF); in isLegalRegOperand() local
5708 if (!SuperRC) in isLegalRegOperand()
5711 DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg()); in isLegalRegOperand()
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| H A D | AMDGPUISelDAGToDAG.cpp | 379 const TargetRegisterClass *SuperRC = in getOperandRegClass() local
384 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC, in getOperandRegClass()
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| H A D | AMDGPUInstructionSelector.cpp | 3012 const TargetRegisterClass *SuperRC, Register IdxReg, in computeIndirectRegIndex() argument
3026 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SuperRC, EltSize); in computeIndirectRegIndex()
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| H A D | SIISelLowering.cpp | 4602 const TargetRegisterClass *SuperRC, in computeIndirectRegAndOffset() argument
4605 int NumElts = TRI.getRegSizeInBits(*SuperRC) / 32; in computeIndirectRegAndOffset()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 584 const TargetRegisterClass *SuperRC = nullptr; in combine() local
586 SuperRC = &Hexagon::DoubleRegsRegClass; in combine()
590 SuperRC = &Hexagon::HvxWRRegClass; in combine()
596 unsigned DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC); in combine()
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| H A D | HexagonRegisterInfo.cpp | 439 if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses()) in getHexagonSubRegIndex() local
440 return getHexagonSubRegIndex(*SuperRC, GenIdx); in getHexagonSubRegIndex()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.h | 437 CodeGenRegisterClass *SuperRC) { in addSuperRegClass() argument
438 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 684 getSubRegisterClass(const TargetRegisterClass *SuperRC, in getSubRegisterClass() argument
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