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Searched refs:SuperRC (Results 1 – 18 of 18) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp610 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
613 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
621 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size())); in FindSuitableFreeRegisters()
623 unsigned OrigR = RenameOrder[SuperRC]; in FindSuitableFreeRegisters()
716 RenameOrder.erase(SuperRC); in FindSuitableFreeRegisters()
717 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R)); in FindSuitableFreeRegisters()
H A DRegAllocGreedy.cpp1473 const MachineInstr *MI, Register Reg, const TargetRegisterClass *SuperRC, in getNumAllocatableRegsForConstraints() argument
1476 assert(SuperRC && "Invalid register class"); in getNumAllocatableRegsForConstraints()
1479 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI, in getNumAllocatableRegsForConstraints()
1575 const TargetRegisterClass *SuperRC = in tryInstructionSplit() local
1578 RegClassInfo.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
1588 getNumAllocatableRegsForConstraints(MI, VirtReg.reg(), SuperRC, in tryInstructionSplit()
H A DTargetLoweringBase.cpp1337 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); in findRepresentativeClass() local
1339 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC)) in findRepresentativeClass()
1341 if (!isLegalRC(*TRI, *SuperRC)) in findRepresentativeClass()
1343 BestRC = SuperRC; in findRepresentativeClass()
H A DSplitKit.cpp612 const TargetRegisterClass *SuperRC = in rematWillIncreaseRestriction() local
617 UseMI->getRegClassConstraintEffectForVReg(DefReg, SuperRC, &TII, &TRI, in rematWillIncreaseRestriction()
H A DMachineVerifier.cpp2757 const TargetRegisterClass *SuperRC = in visitMachineOperand() local
2759 if (!SuperRC) { in visitMachineOperand()
2763 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILoadStoreOptimizer.cpp1296 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in copyFromSrcRegs() local
1297 Register SrcReg = MRI->createVirtualRegister(SuperRC); in copyFromSrcRegs()
1344 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeRead2Pair() local
1345 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeRead2Pair()
1473 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeImagePair() local
1475 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeImagePair()
1509 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeSMemLoadImmPair() local
1511 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeSMemLoadImmPair()
1542 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeBufferLoadPair() local
1545 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeBufferLoadPair()
[all …]
H A DSIRegisterInfo.h301 getCompatibleSubRegClass(const TargetRegisterClass *SuperRC,
H A DSIInstrInfo.h112 const TargetRegisterClass *SuperRC,
117 const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC,
H A DSIRegisterInfo.cpp3629 SIRegisterInfo::getCompatibleSubRegClass(const TargetRegisterClass *SuperRC, in getCompatibleSubRegClass() argument
3634 getMatchingSuperRegClass(SuperRC, SubRC, SubIdx); in getCompatibleSubRegClass()
3635 return MatchRC && MatchRC->hasSubClassEq(SuperRC) ? MatchRC : nullptr; in getCompatibleSubRegClass()
H A DSIInstrInfo.cpp5902 const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, in buildExtractSubReg() argument
5919 const MachineOperand &Op, const TargetRegisterClass *SuperRC, in buildExtractSubRegOrImm() argument
5930 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC, in buildExtractSubRegOrImm()
5959 const TargetRegisterClass *SuperRC = RI.getLargestLegalSuperClass(RC, *MF); in isLegalRegOperand() local
5960 if (!SuperRC) in isLegalRegOperand()
5963 DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg()); in isLegalRegOperand()
H A DAMDGPUISelDAGToDAG.cpp374 const TargetRegisterClass *SuperRC = in getOperandRegClass() local
379 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC, in getOperandRegClass()
H A DAMDGPUInstructionSelector.cpp3206 const TargetRegisterClass *SuperRC, Register IdxReg, in computeIndirectRegIndex() argument
3220 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SuperRC, EltSize); in computeIndirectRegIndex()
H A DSIISelLowering.cpp4826 const TargetRegisterClass *SuperRC, unsigned VecReg, in computeIndirectRegAndOffset() argument
4828 int NumElts = TRI.getRegSizeInBits(*SuperRC) / 32; in computeIndirectRegAndOffset()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonCopyToCombine.cpp577 const TargetRegisterClass *SuperRC = nullptr; in combine() local
579 SuperRC = &Hexagon::DoubleRegsRegClass; in combine()
583 SuperRC = &Hexagon::HvxWRRegClass; in combine()
589 MCRegister DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC); in combine()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.h445 CodeGenRegisterClass *SuperRC) { in addSuperRegClass() argument
446 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
H A DCodeGenRegisters.cpp1106 for (CodeGenRegisterClass *SuperRC : Pair.second) in extendSuperRegClasses()
1107 addSuperRegClass(ComposedSubIdx, SuperRC); in extendSuperRegClasses()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h710 getSubRegisterClass(const TargetRegisterClass *SuperRC, in getSubRegisterClass() argument
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DGlobalISelEmitter.cpp1971 const CodeGenRegisterClass *SuperRC = in inferRegClassFromInstructionPattern() local
1973 if (!SuperRC) in inferRegClassFromInstructionPattern()
1981 SuperRC->getMatchingSubClassWithSubRegs(CGRegs, SubIdx); in inferRegClassFromInstructionPattern()