Searched refs:SuccPred (Results 1 – 3 of 3) sorted by relevance
872 for (MachineBasicBlock *SuccPred : Succ->predecessors()) { in isProfitableToTailDup()873 if (SuccPred == Succ || SuccPred == BB in isProfitableToTailDup()874 || BlockToChain[SuccPred] == &Chain in isProfitableToTailDup()875 || (BlockFilter && !BlockFilter->count(SuccPred))) in isProfitableToTailDup()877 auto Freq = MBFI->getBlockFreq(SuccPred) in isProfitableToTailDup()878 * MBPI->getEdgeProbability(SuccPred, Succ); in isProfitableToTailDup()984 for (auto *SuccPred : Succ->predecessors()) { in isTrellis() local986 if (Successors.count(SuccPred)) { in isTrellis()988 for (MachineBasicBlock *CheckSucc : SuccPred->successors()) in isTrellis()993 const BlockChain *PredChain = BlockToChain[SuccPred]; in isTrellis()[all …]
2868 for (const SDep &SuccPred : SuccSU->Preds) { in canClobberReachingPhysRegUse() local2869 if (!SuccPred.isAssignedRegDep()) in canClobberReachingPhysRegUse()2873 MachineOperand::clobbersPhysReg(RegMask, SuccPred.getReg()) && in canClobberReachingPhysRegUse()2874 scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit())) in canClobberReachingPhysRegUse()2881 if (TRI->regsOverlap(ImpDef, SuccPred.getReg()) && in canClobberReachingPhysRegUse()2882 scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit())) in canClobberReachingPhysRegUse()
1038 for (BasicBlock *SuccPred : SuccPreds) { in CanRedirectPredsOfEmptyBBToSucc()1039 if (BBPreds.count(SuccPred)) { in CanRedirectPredsOfEmptyBBToSucc()1042 CommonPred = SuccPred; in CanRedirectPredsOfEmptyBBToSucc()