| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 2523 // SubVecVT via subregister indices. Returns the subregister index that
2526 // further inserted/extracted within the register class for SubVecVT.
2529 MVT VecVT, MVT SubVecVT, unsigned InsertExtractIdx, in decomposeSubvectorInsertExtractToSubRegs()
2536 unsigned SubRegClassID = getRegClassIDForVecVT(SubVecVT); in decomposeSubvectorInsertExtractToSubRegs()
10016 MVT SubVecVT = SubVec.getSimpleValueType(); in lowerINSERT_SUBVECTOR()
10028 if (SubVecVT.getVectorElementType() == MVT::i1 && in lowerINSERT_SUBVECTOR()
10031 SubVecVT.getVectorMinNumElements() >= 8) { in lowerINSERT_SUBVECTOR()
10034 SubVecVT.getVectorMinNumElements() % 8 == 0 && in lowerINSERT_SUBVECTOR()
10037 SubVecVT = in lowerINSERT_SUBVECTOR()
10038 MVT::getVectorVT(MVT::i8, SubVecVT in lowerINSERT_SUBVECTOR()
2528 decomposeSubvectorInsertExtractToSubRegs(MVT VecVT,MVT SubVecVT,unsigned InsertExtractIdx,const RISCVRegisterInfo * TRI) decomposeSubvectorInsertExtractToSubRegs() argument
10014 MVT SubVecVT = SubVec.getSimpleValueType(); lowerINSERT_SUBVECTOR() local
10249 MVT SubVecVT = Op.getSimpleValueType(); lowerEXTRACT_SUBVECTOR() local
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| H A D | RISCVISelDAGToDAG.cpp | 2175 MVT SubVecVT = SubV.getSimpleValueType(); in Select() local
2178 MVT SubVecContainerVT = SubVecVT; in Select()
2180 if (SubVecVT.isFixedLengthVector()) { in Select()
2181 SubVecContainerVT = TLI.getContainerForFixedLengthVector(SubVecVT); in Select()
2184 Subtarget->expandVScale(SubVecVT.getSizeInBits()) in Select()
2186 assert(isPowerOf2_64(Subtarget->expandVScale(SubVecVT.getSizeInBits()) in Select()
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| H A D | RISCVISelLowering.h | 818 decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 636 EVT SubVecVT = IsExtract ? getTLI()->getValueType(DL, RetTy) in getIntrinsicInstrCost() local
640 if (isUnpackedVectorVT(VecVT) || isUnpackedVectorVT(SubVecVT)) in getIntrinsicInstrCost()
644 getTLI()->getTypeConversion(C, SubVecVT); in getIntrinsicInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1603 EVT SubVecVT = SubVec.getValueType(); in SplitVecRes_INSERT_SUBVECTOR()
1605 unsigned SubElems = SubVecVT.getVectorMinNumElements(); in SplitVecRes_INSERT_SUBVECTOR()
1619 if (VecVT.isScalableVector() == SubVecVT.isScalableVector() && in SplitVecRes_INSERT_SUBVECTOR()
1641 TLI.getVectorSubVecPointer(DAG, StackPtr, VecVT, SubVecVT, Idx); in SplitVecRes_INSERT_SUBVECTOR()
1599 EVT SubVecVT = SubVec.getValueType(); SplitVecRes_INSERT_SUBVECTOR() local
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| H A D | TargetLowering.cpp | 10152 EVT SubVecVT, in getVectorSubVecPointer() argument
10164 assert(SubVecVT.getVectorElementType() == EltVT && in getVectorSubVecPointer()
10167 SubVecVT.getVectorElementCount()); in getVectorSubVecPointer()
10170 if (SubVecVT.isScalableVector()) in getVectorSubVecPointer()
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| H A D | LegalizeIntegerTypes.cpp | 5815 EVT SubVecVT = SubVec.getValueType(); in PromoteIntRes_INSERT_SUBVECTOR() local
5818 SubVecVT.getVectorElementCount()); in PromoteIntRes_INSERT_SUBVECTOR()
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| H A D | DAGCombiner.cpp | 21933 EVT SubVecVT = SubVec.getValueType(); in combineInsertEltToShuffle() local
21935 unsigned NumSrcElts = SubVecVT.getVectorNumElements(); in combineInsertEltToShuffle()
21940 unsigned ExtendRatio = VT.getSizeInBits() / SubVecVT.getSizeInBits(); in combineInsertEltToShuffle()
21957 EVT SubVecEltVT = SubVecVT.getVectorElementType(); in combineInsertEltToShuffle()
21965 SmallVector<SDValue, 8> ConcatOps(ExtendRatio, DAG.getUNDEF(SubVecVT)); in combineInsertEltToShuffle()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 6248 MVT SubVecVT = MVT::getVectorVT(EltTy, 2); in lowerLaneOp() local
6252 Src0SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, SubVecVT, Src0, in lowerLaneOp()
6256 Src1SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, SubVecVT, Src1, in lowerLaneOp()
6260 Src2SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, SubVecVT, Src2, in lowerLaneOp()
6265 ? createLaneOp(Src0SubVec, Src1SubVec, Src2, SubVecVT) in lowerLaneOp()
6266 : createLaneOp(Src0SubVec, Src1, Src2SubVec, SubVecVT)); in lowerLaneOp()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 5429 EVT SubVecVT, SDValue Index) const;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 4358 MVT SubVecVT = SubVec.getSimpleValueType(); in insert1BitVector() local
4359 unsigned SubVecNumElems = SubVecVT.getVectorNumElements(); in insert1BitVector()
4361 IdxVal % SubVecVT.getSizeInBits() == 0 && in insert1BitVector()
4418 Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVecVT, Vec, ZeroIdx); in insert1BitVector()
49608 EVT SubVecVT = SubVec.getValueType(); in combineScalarAndWithMaskSetcc() local
49611 if (!TLI.isTypeLegal(SubVecVT) || in combineScalarAndWithMaskSetcc()
49612 !C1->getAPIntValue().isMask(SubVecVT.getVectorNumElements())) in combineScalarAndWithMaskSetcc()
49637 DAG.getConstant(0, dl, SubVecVT)); in combineScalarAndWithMaskSetcc()
56791 MVT SubVecVT = SubVec.getSimpleValueType(); in combineINSERT_SUBVECTOR() local
56824 SubVecVT.getFixedSizeInBits()) in combineINSERT_SUBVECTOR()
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