| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUPromoteAlloca.cpp | 567 auto *SubVecTy = FixedVectorType::get(VecEltTy, NumLoadedElts); in promoteAllocaUserToVector() local
568 assert(DL.getTypeStoreSize(SubVecTy) == DL.getTypeStoreSize(AccessTy)); in promoteAllocaUserToVector()
570 Value *SubVec = PoisonValue::get(SubVecTy); in promoteAllocaUserToVector()
580 else if (SubVecTy->isPtrOrPtrVectorTy()) in promoteAllocaUserToVector()
581 SubVec = CreateTempPtrIntCast(SubVec, SubVecTy); in promoteAllocaUserToVector()
624 auto *SubVecTy = FixedVectorType::get(VecEltTy, NumWrittenElts); in promoteAllocaUserToVector() local
625 assert(DL.getTypeStoreSize(SubVecTy) == DL.getTypeStoreSize(AccessTy)); in promoteAllocaUserToVector()
627 if (SubVecTy->isPtrOrPtrVectorTy()) in promoteAllocaUserToVector()
628 Val = CreateTempPtrIntCast(Val, SubVecTy); in promoteAllocaUserToVector()
632 Val = Builder.CreateBitOrPointerCast(Val, SubVecTy); in promoteAllocaUserToVector()
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| H A D | AMDGPUCodeGenPrepare.cpp | 2066 Type *SubVecTy = FixedVectorType::get(EltTy, SubVecSize); in visitPHINode() local
2069 Slices.emplace_back(SubVecTy, Idx, SubVecSize); in visitPHINode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InterleavedAccess.cpp | 165 Instruction *VecInst, unsigned NumSubVectors, FixedVectorType *SubVecTy, in decompose() argument
174 DL.getTypeSizeInBits(SubVecTy) * NumSubVectors && in decompose()
186 createSequentialMask(Indices[i], SubVecTy->getNumElements(), in decompose()
204 VecBaseTy = SubVecTy; in decompose()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 1632 auto *SubVecTy = in getInterleavedMemoryOpCost() local
1641 TLI->isLegalInterleavedAccessType(Factor, SubVecTy, Alignment, DL)) in getInterleavedMemoryOpCost()
1642 return Factor * BaseCost * TLI->getNumInterleavedAccesses(SubVecTy, DL); in getInterleavedMemoryOpCost()
1651 DL.getTypeSizeInBits(SubVecTy).getFixedValue() <= 64) in getInterleavedMemoryOpCost()
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| H A D | ARMISelLowering.cpp | 21757 auto *SubVecTy = FixedVectorType::get(EltTy, LaneLen); in lowerInterleavedStore() local
21765 if (!isLegalInterleavedAccessType(Factor, SubVecTy, Alignment, DL)) in lowerInterleavedStore()
21768 unsigned NumStores = getNumInterleavedAccesses(SubVecTy, DL); in lowerInterleavedStore()
21785 SubVecTy = FixedVectorType::get(IntTy, LaneLen); in lowerInterleavedStore()
21795 SubVecTy = FixedVectorType::get(SubVecTy->getElementType(), LaneLen); in lowerInterleavedStore()
21798 assert(isTypeLegal(EVT::getEVT(SubVecTy)) && "Illegal vstN vector type!"); in lowerInterleavedStore()
21809 Type *Tys[] = {PtrTy, SubVecTy}; in lowerInterleavedStore()
21822 Type *Tys[] = {PtrTy, SubVecTy}; in lowerInterleavedStore()
21839 BaseAddr = Builder.CreateConstGEP1_32(SubVecTy->getElementType(), in lowerInterleavedStore()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.cpp | 991 auto *SubVecTy = in getInterleavedMemoryOpCost() local
995 TLI->isLegalInterleavedAccessType(SubVecTy, Factor, Alignment, in getInterleavedMemoryOpCost()
1003 MVT SubVecVT = getTLI()->getValueType(DL, SubVecTy).getSimpleVT(); in getInterleavedMemoryOpCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCalls.cpp | 3508 auto *SubVecTy = dyn_cast<FixedVectorType>(SubVec->getType()); in visitCallInst() local
3512 if (DstTy && VecTy && SubVecTy) { in visitCallInst()
3515 unsigned SubVecNumElts = SubVecTy->getNumElements(); in visitCallInst()
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| /freebsd/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | riscv_vector.td | 1757 // C/C++ Operand: SubVecTy, IR Operand: VecTy, SubVecTy, Index
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 3472 LLT SubVecTy = MRI.getType(SubVec); in widenScalar() local
3473 LLT SubVecWideTy = SubVecTy.changeElementType(WideTy.getElementType()); in widenScalar()
4008 LLT SubVecTy = MRI.getType(SubVec); in bitcastInsertSubvector() local
4018 ElementCount SubVecTyEC = SubVecTy.getElementCount(); in bitcastInsertSubvector()
4035 SubVecTy = LLT::vector(SubVecTyEC.divideCoefficientBy(AdjustAmt), AdjustAmt); in bitcastInsertSubvector()
4037 auto CastSubVec = MIRBuilder.buildBitcast(SubVecTy, SubVec); in bitcastInsertSubvector()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 6306 auto *SubVecTy = getWidenedType(ScalarTy, VF); in canVectorizeLoads() local
6315 SubVecTy) in canVectorizeLoads()
6326 TTI, ScalarTy, SubVecTy, APInt::getAllOnes(VF), in canVectorizeLoads()
6331 TTI, ScalarTy, SubVecTy, APInt::getOneBitSet(VF, 0), in canVectorizeLoads()
6333 ::getShuffleCost(TTI, TTI::SK_Broadcast, SubVecTy, {}, in canVectorizeLoads()
6339 TTI.getMemoryOpCost(Instruction::Load, SubVecTy, LI0->getAlign(), in canVectorizeLoads()
6345 VecLdCost += TTI.getStridedMemoryOpCost(Instruction::Load, SubVecTy, in canVectorizeLoads()
6353 Instruction::Load, SubVecTy, CommonAlignment, in canVectorizeLoads()
6356 ::getShuffleCost(TTI, TTI::SK_PermuteSingleSrc, SubVecTy, in canVectorizeLoads()
6360 VecLdCost += TTI.getGatherScatterOpCost(Instruction::Load, SubVecTy, in canVectorizeLoads()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 4618 auto *SubVecTy = in getInterleavedMemoryOpCost() local
4627 TLI->isLegalInterleavedAccessType(SubVecTy, DL, UseScalable)) in getInterleavedMemoryOpCost()
4628 return Factor * TLI->getNumInterleavedAccesses(SubVecTy, DL, UseScalable); in getInterleavedMemoryOpCost()
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| H A D | AArch64ISelLowering.cpp | 17341 auto *SubVecTy = FixedVectorType::get(EltTy, LaneLen); in lowerInterleavedStore() local
17349 if (!isLegalInterleavedAccessType(SubVecTy, DL, UseScalable)) in lowerInterleavedStore()
17352 unsigned NumStores = getNumInterleavedAccesses(SubVecTy, DL, UseScalable); in lowerInterleavedStore()
17370 SubVecTy = FixedVectorType::get(IntTy, LaneLen); in lowerInterleavedStore()
17376 SubVecTy = FixedVectorType::get(SubVecTy->getElementType(), LaneLen); in lowerInterleavedStore()
17378 auto *STVTy = UseScalable ? cast<VectorType>(getSVEContainerIRType(SubVecTy)) in lowerInterleavedStore()
17379 : SubVecTy; in lowerInterleavedStore()
17396 if (Factor == 2 && SubVecTy->getPrimitiveSizeInBits() == 64 && in lowerInterleavedStore()
17414 getSVEPredPatternFromNumElements(SubVecTy->getNumElements()); in lowerInterleavedStore()
17418 DL.getTypeSizeInBits(SubVecTy)) in lowerInterleavedStore()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | Verifier.cpp | 6399 VectorType *SubVecTy = cast<VectorType>(SubVec->getType()); in visitIntrinsicCall() local
6402 ElementCount SubVecEC = SubVecTy->getElementCount(); in visitIntrinsicCall()
6403 Check(VecTy->getElementType() == SubVecTy->getElementType(), in visitIntrinsicCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 1241 MVT SubVecTy = tyVector(ty(Ext), ElemTy); in insertHvxElementReg() local
1242 SDValue Ins = insertVector(DAG.getBitcast(SubVecTy, Ext), in insertHvxElementReg()
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