| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUPromoteAlloca.cpp | 520 auto *SubVecTy = FixedVectorType::get(VecEltTy, NumLoadedElts); in promoteAllocaUserToVector() local
521 assert(DL.getTypeStoreSize(SubVecTy) == DL.getTypeStoreSize(AccessTy)); in promoteAllocaUserToVector()
523 Value *SubVec = PoisonValue::get(SubVecTy); in promoteAllocaUserToVector()
533 else if (SubVecTy->isPtrOrPtrVectorTy()) in promoteAllocaUserToVector()
534 SubVec = CreateTempPtrIntCast(SubVec, SubVecTy); in promoteAllocaUserToVector()
577 auto *SubVecTy = FixedVectorType::get(VecEltTy, NumWrittenElts); in promoteAllocaUserToVector() local
578 assert(DL.getTypeStoreSize(SubVecTy) == DL.getTypeStoreSize(AccessTy)); in promoteAllocaUserToVector()
580 if (SubVecTy->isPtrOrPtrVectorTy()) in promoteAllocaUserToVector()
581 Val = CreateTempPtrIntCast(Val, SubVecTy); in promoteAllocaUserToVector()
585 Val = Builder.CreateBitOrPointerCast(Val, SubVecTy); in promoteAllocaUserToVector()
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| H A D | AMDGPUCodeGenPrepare.cpp | 1970 Type *SubVecTy = FixedVectorType::get(EltTy, SubVecSize); in visitPHINode() local
1973 Slices.emplace_back(SubVecTy, Idx, SubVecSize); in visitPHINode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InterleavedAccess.cpp | 168 Instruction *VecInst, unsigned NumSubVectors, FixedVectorType *SubVecTy, in decompose() argument
177 DL.getTypeSizeInBits(SubVecTy) * NumSubVectors && in decompose()
189 createSequentialMask(Indices[i], SubVecTy->getNumElements(), in decompose()
207 VecBaseTy = SubVecTy; in decompose()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.cpp | 447 auto *SubVecTy = FixedVectorType::get(Tp->getElementType(), SubVF); in getShuffleCost() local
462 SubVecTy, SubMask, CostKind, 0, nullptr); in getShuffleCost()
639 auto *SubVecTy = in getInterleavedMemoryOpCost() local
644 TLI->isLegalInterleavedAccessType(SubVecTy, Factor, Alignment, in getInterleavedMemoryOpCost()
677 FixedVectorType *SubVecTy = in getInterleavedMemoryOpCost() local
681 getShuffleCost(TTI::ShuffleKind::SK_PermuteSingleSrc, SubVecTy, Mask, in getInterleavedMemoryOpCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 1549 auto *SubVecTy = in getInterleavedMemoryOpCost() local
1558 TLI->isLegalInterleavedAccessType(Factor, SubVecTy, Alignment, DL)) in getInterleavedMemoryOpCost()
1559 return Factor * BaseCost * TLI->getNumInterleavedAccesses(SubVecTy, DL); in getInterleavedMemoryOpCost()
1568 DL.getTypeSizeInBits(SubVecTy).getFixedValue() <= 64) in getInterleavedMemoryOpCost()
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| H A D | ARMISelLowering.cpp | 21832 auto *SubVecTy = FixedVectorType::get(EltTy, LaneLen); in lowerInterleavedStore() local
21840 if (!isLegalInterleavedAccessType(Factor, SubVecTy, Alignment, DL)) in lowerInterleavedStore()
21843 unsigned NumStores = getNumInterleavedAccesses(SubVecTy, DL); in lowerInterleavedStore()
21860 SubVecTy = FixedVectorType::get(IntTy, LaneLen); in lowerInterleavedStore()
21870 SubVecTy = FixedVectorType::get(SubVecTy->getElementType(), LaneLen); in lowerInterleavedStore()
21873 assert(isTypeLegal(EVT::getEVT(SubVecTy)) && "Illegal vstN vector type!"); in lowerInterleavedStore()
21884 Type *Tys[] = {PtrTy, SubVecTy}; in lowerInterleavedStore()
21900 Type *Tys[] = {PtrTy, SubVecTy}; in lowerInterleavedStore()
21919 BaseAddr = Builder.CreateConstGEP1_32(SubVecTy->getElementType(), in lowerInterleavedStore()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCalls.cpp | 3211 auto *SubVecTy = dyn_cast<FixedVectorType>(SubVec->getType()); in visitCallInst() local
3215 if (DstTy && VecTy && SubVecTy) { in visitCallInst()
3218 unsigned SubVecNumElts = SubVecTy->getNumElements(); in visitCallInst()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 3525 auto *SubVecTy = in getInterleavedMemoryOpCost() local
3534 TLI->isLegalInterleavedAccessType(SubVecTy, DL, UseScalable)) in getInterleavedMemoryOpCost()
3535 return Factor * TLI->getNumInterleavedAccesses(SubVecTy, DL, UseScalable); in getInterleavedMemoryOpCost()
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| H A D | AArch64ISelLowering.cpp | 16919 auto *SubVecTy = FixedVectorType::get(EltTy, LaneLen); in lowerInterleavedStore() local
16927 if (!isLegalInterleavedAccessType(SubVecTy, DL, UseScalable)) in lowerInterleavedStore()
16930 unsigned NumStores = getNumInterleavedAccesses(SubVecTy, DL, UseScalable); in lowerInterleavedStore()
16948 SubVecTy = FixedVectorType::get(IntTy, LaneLen); in lowerInterleavedStore()
16954 SubVecTy = FixedVectorType::get(SubVecTy->getElementType(), LaneLen); in lowerInterleavedStore()
16956 auto *STVTy = UseScalable ? cast<VectorType>(getSVEContainerIRType(SubVecTy)) in lowerInterleavedStore()
16957 : SubVecTy; in lowerInterleavedStore()
16974 if (Factor == 2 && SubVecTy->getPrimitiveSizeInBits() == 64 && in lowerInterleavedStore()
16992 getSVEPredPatternFromNumElements(SubVecTy->getNumElements()); in lowerInterleavedStore()
16996 DL.getTypeSizeInBits(SubVecTy)) in lowerInterleavedStore()
[all …]
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| /freebsd/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | riscv_vector.td | 2448 // C/C++ Operand: SubVecTy, IR Operand: VecTy, SubVecTy, Index
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 4694 auto *SubVecTy = getWidenedType(ScalarTy, VF); in canVectorizeLoads() local
4702 CostKind, ScalarTy, SubVecTy); in canVectorizeLoads()
4704 Instruction::Load, SubVecTy, LI0->getAlign(), in canVectorizeLoads()
4714 CostKind, ScalarTy, SubVecTy); in canVectorizeLoads()
4717 Instruction::Load, SubVecTy, LI0->getPointerOperand(), in canVectorizeLoads()
4726 CostKind, ScalarTy, SubVecTy); in canVectorizeLoads()
4729 Instruction::Load, SubVecTy, LI0->getPointerOperand(), in canVectorizeLoads()
4743 CostKind, I * VF, SubVecTy); in canVectorizeLoads()
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| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | Verifier.cpp | 6113 VectorType *SubVecTy = cast<VectorType>(SubVec->getType()); in visitIntrinsicCall() local
6116 ElementCount SubVecEC = SubVecTy->getElementCount(); in visitIntrinsicCall()
6117 Check(VecTy->getElementType() == SubVecTy->getElementType(), in visitIntrinsicCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 1230 MVT SubVecTy = tyVector(ty(Ext), ElemTy); in insertHvxElementReg()
1231 SDValue Ins = insertVector(DAG.getBitcast(SubVecTy, Ext), in insertHvxElementReg() local
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