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Searched refs:SubRegIdx (Results 1 – 25 of 33) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRenameIndependentSubregs.cpp182 unsigned SubRegIdx = MO.getSubReg(); in findComponents() local
183 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findComponents()
226 unsigned SubRegIdx = MO.getSubReg(); in rewriteOperands() local
227 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in rewriteOperands()
355 unsigned SubRegIdx = MO.getSubReg(); in computeMainRangesFixFlags() local
356 if (SubRegIdx == 0) in computeMainRangesFixFlags()
H A DRegisterPressure.cpp533 unsigned SubRegIdx = MO.getSubReg(); in collectOperandLanes() local
536 pushRegLanes(Reg, SubRegIdx, RegOpers.Uses); in collectOperandLanes()
541 SubRegIdx = 0; in collectOperandLanes()
545 pushRegLanes(Reg, SubRegIdx, RegOpers.DeadDefs); in collectOperandLanes()
547 pushRegLanes(Reg, SubRegIdx, RegOpers.Defs); in collectOperandLanes()
551 void pushRegLanes(Register Reg, unsigned SubRegIdx, in pushRegLanes() argument
554 LaneBitmask LaneMask = SubRegIdx != 0 in pushRegLanes()
555 ? TRI.getSubRegIndexLaneMask(SubRegIdx) in pushRegLanes()
1235 unsigned SubRegIdx = MO.getSubReg(); in findUseBetween() local
1236 LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findUseBetween()
H A DVirtRegMap.cpp396 unsigned SubRegIdx = MO.getSubReg(); in readsUndefSubreg() local
397 assert(SubRegIdx != 0 && LI.hasSubRanges()); in readsUndefSubreg()
398 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx); in readsUndefSubreg()
H A DStackMaps.cpp286 unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg()); in print()
287 if (SubRegIdx) in print()
288 Offset = TRI->getSubRegIdxOffset(SubRegIdx); in print()
271 unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg()); parseOperand() local
H A DMachineCopyPropagation.cpp715 unsigned SubRegIdx = TRI->getSubRegIndex(CopyDstReg, MOUse.getReg()); in forwardUses() local
716 assert(SubRegIdx && in forwardUses()
718 ForwardedReg = TRI->getSubReg(CopySrcReg, SubRegIdx); in forwardUses()
721 << TRI->getSubRegIndexName(SubRegIdx) << '\n'); in forwardUses()
H A DRegAllocFast.cpp998 unsigned SubRegIdx = MO.getSubReg(); in allocVirtRegUndef() local
999 if (SubRegIdx != 0) { in allocVirtRegUndef()
1000 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx); in allocVirtRegUndef()
H A DMachineVerifier.cpp2797 const unsigned SubRegIdx = MO->getSubReg(); in checkLiveness() local
2803 if (SubRegIdx != 0 && (MO->isDef() || !MO->isUndef()) && !LI->empty() && in checkLiveness()
2851 LaneBitmask MOMask = SubRegIdx != 0 in checkLiveness()
2852 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
2949 LaneBitmask MOMask = SubRegIdx != 0 in checkLiveness()
2950 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
H A DRegisterCoalescer.cpp319 MachineOperand &MO, unsigned SubRegIdx);
1791 MachineOperand &MO, unsigned SubRegIdx) { in addUndefFlag() argument
1792 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubRegIdx); in addUndefFlag()
1945 unsigned SubRegIdx = MO.getSubReg(); in setUndefOnPrunedSubRegUses() local
1946 if (SubRegIdx == 0 || MO.isUndef()) in setUndefOnPrunedSubRegUses()
1949 LaneBitmask SubRegMask = TRI->getSubRegIndexLaneMask(SubRegIdx); in setUndefOnPrunedSubRegUses()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.cpp318 unsigned Opcode, SubRegIdx; in lowerVSPILL() local
324 SubRegIdx = RISCV::sub_vrm1_0; in lowerVSPILL()
328 SubRegIdx = RISCV::sub_vrm2_0; in lowerVSPILL()
332 SubRegIdx = RISCV::sub_vrm4_0; in lowerVSPILL()
367 .addReg(TRI->getSubReg(SrcReg, SubRegIdx + I)) in lowerVSPILL()
395 unsigned Opcode, SubRegIdx; in lowerVRELOAD() local
401 SubRegIdx = RISCV::sub_vrm1_0; in lowerVRELOAD()
405 SubRegIdx = RISCV::sub_vrm2_0; in lowerVRELOAD()
409 SubRegIdx = RISCV::sub_vrm4_0; in lowerVRELOAD()
440 TRI->getSubReg(DestReg, SubRegIdx + I)) in lowerVRELOAD()
H A DRISCVISelDAGToDAG.cpp370 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); in selectVLSEG() local
372 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLSEG()
411 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); in selectVLSEGFF() local
413 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLSEGFF()
463 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); in selectVLXSEG() local
465 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLXSEG()
2195 unsigned SubRegIdx; in Select() local
2196 std::tie(SubRegIdx, Idx) = in Select()
2217 if (SubRegIdx == RISCV::NoSubRegister) { in Select()
2230 SDValue Insert = CurDAG->getTargetInsertSubreg(SubRegIdx, DL, VT, V, SubV); in Select()
[all …]
H A DRISCVISelLowering.cpp2543 unsigned SubRegIdx = RISCV::NoSubRegister; in decomposeSubvectorInsertExtractToSubRegs()
2550 SubRegIdx = TRI->composeSubRegIndices(SubRegIdx, in decomposeSubvectorInsertExtractToSubRegs()
2555 return {SubRegIdx, InsertExtractIdx}; in decomposeSubvectorInsertExtractToSubRegs()
8493 unsigned SubRegIdx = OrigIdx / ElemsPerVReg; in lowerINSERT_VECTOR_ELT()
8495 SubRegIdx * M1VT.getVectorElementCount().getKnownMinValue(); in lowerINSERT_VECTOR_ELT()
8704 unsigned SubRegIdx = OrigIdx / ElemsPerVReg; in lowerEXTRACT_VECTOR_ELT()
8706 SubRegIdx * M1VT.getVectorElementCount().getKnownMinValue(); in lowerEXTRACT_VECTOR_ELT()
10126 unsigned SubRegIdx; in lowerINSERT_SUBVECTOR()
10137 SubRegIdx in lowerINSERT_SUBVECTOR()
2542 unsigned SubRegIdx = RISCV::NoSubRegister; decomposeSubvectorInsertExtractToSubRegs() local
8491 unsigned SubRegIdx = OrigIdx / ElemsPerVReg; lowerINSERT_VECTOR_ELT() local
8702 unsigned SubRegIdx = OrigIdx / ElemsPerVReg; lowerEXTRACT_VECTOR_ELT() local
10124 unsigned SubRegIdx; lowerINSERT_SUBVECTOR() local
10347 unsigned SubRegIdx; lowerEXTRACT_SUBVECTOR() local
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRewritePartialRegUses.cpp144 unsigned SubRegIdx) const;
188 unsigned SubRegIdx) const { in getSuperRegClassMask()
190 SuperRegMasks.try_emplace({RC, SubRegIdx}, nullptr); in getSuperRegClassMask()
193 if (RCI.getSubReg() == SubRegIdx) { in getSuperRegClassMask()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrGISel.td518 SubRegIndex SubRegIdx, Operand IndexType,
522 (STR (EXTRACT_SUBREG VecListOne64:$Vt, SubRegIdx),
527 SubRegIndex SubRegIdx, Instruction STR> {
528 defm : VecStoreLane64_0Pat<am_unscaled64, StoreOp, VTy, STy, SubRegIdx, simm9, STR>;
533 SubRegIndex SubRegIdx,
538 (STRW (EXTRACT_SUBREG VecListOne64:$Vt, SubRegIdx),
543 (STRX (EXTRACT_SUBREG VecListOne64:$Vt, SubRegIdx),
H A DAArch64ISelDAGToDAG.cpp376 unsigned SubRegIdx);
378 unsigned SubRegIdx);
1679 unsigned SubRegIdx) { in SelectLoad() argument
1693 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1708 unsigned Opc, unsigned SubRegIdx) { in SelectPostLoad() argument
1732 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp330 const unsigned *SubRegIdx, in copyPhysSubRegs() argument
335 Register SubDest = TRI->getSubReg(DestReg, SubRegIdx[Idx]); in copyPhysSubRegs()
336 Register SubSrc = TRI->getSubReg(SrcReg, SubRegIdx[Idx]); in copyPhysSubRegs()
393 const unsigned SubRegIdx[] = {VE::sub_vm_even, VE::sub_vm_odd}; in copyPhysReg() local
396 NumSubRegs, SubRegIdx, &getRegisterInfo()); in copyPhysReg()
399 const unsigned SubRegIdx[] = {VE::sub_even, VE::sub_odd}; in copyPhysReg() local
402 NumSubRegs, SubRegIdx, &getRegisterInfo()); in copyPhysReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupBWInsts.cpp189 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg); in getSuperRegDestIfDead() local
195 if (SubRegIdx == X86::sub_8bit_hi) in getSuperRegDestIfDead()
H A DX86ISelDAGToDAG.cpp1692 unsigned SubRegIdx = N->getConstantOperandVal(2); in PostprocessISelDAG() local
1693 if (SubRegIdx != X86::sub_xmm && SubRegIdx != X86::sub_ymm) in PostprocessISelDAG()
6038 unsigned SubRegIdx; in Select() local
6054 SubRegIdx = 0; in Select()
6062 SubRegIdx = 0; in Select()
6071 SubRegIdx = X86::sub_8bit; in Select()
6077 SubRegIdx = X86::sub_16bit; in Select()
6083 SubRegIdx = X86::sub_32bit; in Select()
6094 if (SubRegIdx != 0) { in Select()
6096 CurDAG->getTargetExtractSubreg(SubRegIdx, dl, SubRegVT, Shift); in Select()
H A DX86InstrAVX512.td2972 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
2973 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx)),
2982 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
2983 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx)),
2996 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3006 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3015 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3025 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3037 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3038 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx)),
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DGIMatchTableExecutorImpl.h1106 uint16_t SubRegIdx = readU16(); in executeMatchTable() local
1109 0, SubRegIdx); in executeMatchTable()
1113 << OpIdx << ", " << SubRegIdx << ")\n"); in executeMatchTable()
1290 uint16_t SubRegIdx = readU16(); in executeMatchTable() local
1294 MI->getOperand(MI->getNumOperands() - 1).setSubReg(SubRegIdx); in executeMatchTable()
1299 << RenderOpID << ", " << SubRegIdx << ")\n"); in executeMatchTable()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp487 CodeGenSubRegIndex *SubRegIdx; in computeSecondarySubRegs() local
489 std::tie(SubRegIdx, SubReg) = SubRegQueue.front(); in computeSecondarySubRegs()
507 assert(getSubRegIndex(SubReg) == SubRegIdx && "LeadingSuperRegs correct"); in computeSecondarySubRegs()
509 if (CodeGenSubRegIndex *SubRegIdx = getSubRegIndex(SubReg)) { in computeSecondarySubRegs() local
510 if (SubRegIdx->ConcatenationOf.empty()) in computeSecondarySubRegs()
511 Parts.push_back(SubRegIdx); in computeSecondarySubRegs()
513 append_range(Parts, SubRegIdx->ConcatenationOf); in computeSecondarySubRegs()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/GlobalISel/
H A DGlobalISelMatchTable.cpp1998 const bool NeedsFlags = (SubRegIdx || IsDef); in emitRenderOpcodes()
1999 if (SubRegIdx) { in emitRenderOpcodes()
2025 if (SubRegIdx) in emitRenderOpcodes()
2026 Table << MatchTable::NamedValue(2, SubRegIdx->getQualifiedName()); in emitRenderOpcodes()
2059 ImmRenderer::emitAddImm(Table, Rule, InsnID, SubRegIdx->EnumValue, in emitRenderOpcodes()
H A DGlobalISelMatchTable.h2074 const CodeGenSubRegIndex *SubRegIdx; variable
2083 SubRegIdx(SubReg), IsDef(IsDef), IsDead(IsDead) {} in OperandRenderer()
2124 const CodeGenSubRegIndex *SubRegIdx; variable
2128 : OperandRenderer(OR_SubRegIndex), InsnID(InsnID), SubRegIdx(SRI) {} in SubRegIndexRenderer()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp2138 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32); in ExtendToInt64() local
2143 SubRegIdx), 0); in ExtendToInt64()
2152 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32); in TruncateToInt32() local
2154 MVT::i32, V, SubRegIdx), 0); in TruncateToInt32()
3223 SDValue SubRegIdx = in addExtOrTrunc() local
3226 ImDef, NatWidthRes, SubRegIdx), 0); in addExtOrTrunc()
3233 SDValue SubRegIdx = in addExtOrTrunc() local
3236 NatWidthRes, SubRegIdx), 0); in addExtOrTrunc()
5394 SDValue SubRegIdx = CurDAG->getTargetConstant(SubReg, dl, MVT::i32); in Select() local
5397 CR6Reg, SubRegIdx, BCDOp.getValue(1)), in Select()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h685 unsigned SubRegIdx) const { in getSubRegisterClass() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp1198 unsigned SubRegIdx = in loadVectorConstant() local
1201 Node, CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, Op).getNode()); in loadVectorConstant()

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