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Searched refs:SubRegIdx (Results 1 – 25 of 38) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRenameIndependentSubregs.cpp188 unsigned SubRegIdx = MO.getSubReg(); in findComponents() local
189 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findComponents()
232 unsigned SubRegIdx = MO.getSubReg(); in rewriteOperands() local
233 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in rewriteOperands()
361 unsigned SubRegIdx = MO.getSubReg(); in computeMainRangesFixFlags() local
362 if (SubRegIdx == 0) in computeMainRangesFixFlags()
H A DRegisterPressure.cpp528 unsigned SubRegIdx = MO.getSubReg(); in collectOperandLanes() local
531 pushRegLanes(Reg, SubRegIdx, RegOpers.Uses); in collectOperandLanes()
536 SubRegIdx = 0; in collectOperandLanes()
540 pushRegLanes(Reg, SubRegIdx, RegOpers.DeadDefs); in collectOperandLanes()
542 pushRegLanes(Reg, SubRegIdx, RegOpers.Defs); in collectOperandLanes()
546 void pushRegLanes(Register Reg, unsigned SubRegIdx, in pushRegLanes() argument
549 LaneBitmask LaneMask = SubRegIdx != 0 in pushRegLanes()
550 ? TRI.getSubRegIndexLaneMask(SubRegIdx) in pushRegLanes()
1223 unsigned SubRegIdx = MO.getSubReg(); in findUseBetween() local
1224 LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findUseBetween()
H A DVirtRegMap.cpp466 unsigned SubRegIdx = MO.getSubReg(); in readsUndefSubreg() local
467 assert(SubRegIdx != 0 && LI.hasSubRanges()); in readsUndefSubreg()
468 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx); in readsUndefSubreg()
H A DStackMaps.cpp279 unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg()); in parseOperand() local
280 if (SubRegIdx) in parseOperand()
281 Offset = TRI->getSubRegIdxOffset(SubRegIdx); in parseOperand()
H A DMachineCopyPropagation.cpp818 unsigned SubRegIdx = TRI->getSubRegIndex(CopyDstReg, MOUse.getReg()); in forwardUses() local
819 assert(SubRegIdx && in forwardUses()
821 ForwardedReg = TRI->getSubReg(CopySrcReg, SubRegIdx); in forwardUses()
824 << TRI->getSubRegIndexName(SubRegIdx) << '\n'); in forwardUses()
H A DRegAllocFast.cpp1022 unsigned SubRegIdx = MO.getSubReg(); in allocVirtRegUndef() local
1023 if (SubRegIdx != 0) { in allocVirtRegUndef()
1024 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx); in allocVirtRegUndef()
H A DRegisterCoalescer.cpp319 MachineOperand &MO, unsigned SubRegIdx);
1848 MachineOperand &MO, unsigned SubRegIdx) { in addUndefFlag() argument
1849 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubRegIdx); in addUndefFlag()
2005 unsigned SubRegIdx = MO.getSubReg(); in setUndefOnPrunedSubRegUses() local
2006 if (SubRegIdx == 0 || MO.isUndef()) in setUndefOnPrunedSubRegUses()
2009 LaneBitmask SubRegMask = TRI->getSubRegIndexLaneMask(SubRegIdx); in setUndefOnPrunedSubRegUses()
H A DMachineVerifier.cpp2944 const unsigned SubRegIdx = MO->getSubReg(); in checkLiveness() local
2950 if (SubRegIdx != 0 && (MO->isDef() || !MO->isUndef()) && !LI->empty() && in checkLiveness()
2998 LaneBitmask MOMask = SubRegIdx != 0 in checkLiveness()
2999 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
3101 LaneBitmask MOMask = SubRegIdx != 0 in checkLiveness()
3102 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRewritePartialRegUses.cpp108 unsigned SubRegIdx) const;
174 const TargetRegisterClass *RC, unsigned SubRegIdx) const { in getSuperRegClassMask()
176 SuperRegMasks.try_emplace({RC, SubRegIdx}, nullptr); in getSuperRegClassMask()
179 if (RCI.getSubReg() == SubRegIdx) { in getSuperRegClassMask()
H A DSIFoldOperands.cpp929 unsigned SubRegIdx = RegSeq.getOperand(I + 1).getImm(); in getRegSeqInit() local
940 Defs.emplace_back(&SrcOp, SubRegIdx); in getRegSeqInit()
946 Defs.emplace_back(DefSrc, SubRegIdx); in getRegSeqInit()
950 Defs.emplace_back(&SrcOp, SubRegIdx); in getRegSeqInit()
1311 unsigned SubRegIdx = OpToFold.getSubReg(); in foldOperand() local
1330 if (SubRegIdx > AMDGPU::sub1) { in foldOperand()
1331 LaneBitmask M = TRI->getSubRegIndexLaneMask(SubRegIdx); in foldOperand()
1337 SubRegIdx = Indexes[0]; in foldOperand()
1340 SubRegIdx = 0; in foldOperand()
1342 SubRegIdx = AMDGPU::sub0; in foldOperand()
[all …]
H A DGCNRegPressure.cpp355 unsigned SubRegIdx = MO.getSubReg(); in findUseBetween() local
356 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx); in findUseBetween()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.cpp407 unsigned Opcode, SubRegIdx; in lowerVSPILL() local
413 SubRegIdx = RISCV::sub_vrm1_0; in lowerVSPILL()
417 SubRegIdx = RISCV::sub_vrm2_0; in lowerVSPILL()
421 SubRegIdx = RISCV::sub_vrm4_0; in lowerVSPILL()
462 .addReg(TRI->getSubReg(SrcReg, SubRegIdx + I)) in lowerVSPILL()
490 unsigned Opcode, SubRegIdx; in lowerVRELOAD() local
496 SubRegIdx = RISCV::sub_vrm1_0; in lowerVRELOAD()
500 SubRegIdx = RISCV::sub_vrm2_0; in lowerVRELOAD()
504 SubRegIdx = RISCV::sub_vrm4_0; in lowerVRELOAD()
540 TRI->getSubReg(DestReg, SubRegIdx + I)) in lowerVRELOAD()
H A DRISCVISelDAGToDAG.cpp2545 unsigned SubRegIdx; in Select() local
2546 std::tie(SubRegIdx, Idx) = in Select()
2569 if (SubRegIdx == RISCV::NoSubRegister) { in Select()
2582 SDValue Insert = CurDAG->getTargetInsertSubreg(SubRegIdx, DL, VT, V, SubV); in Select()
2604 unsigned SubRegIdx; in Select() local
2605 std::tie(SubRegIdx, Idx) = in Select()
2617 if (SubRegIdx == RISCV::NoSubRegister) { in Select()
2629 SDValue Extract = CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, V); in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrGISel.td461 SubRegIndex SubRegIdx, Operand IndexType,
465 (STR (EXTRACT_SUBREG VecListOne64:$Vt, SubRegIdx),
470 SubRegIndex SubRegIdx, Instruction STR> {
471 defm : VecStoreLane64_0Pat<am_unscaled64, StoreOp, VTy, STy, SubRegIdx, simm9, STR>;
476 SubRegIndex SubRegIdx,
481 (STRW (EXTRACT_SUBREG VecListOne64:$Vt, SubRegIdx),
486 (STRX (EXTRACT_SUBREG VecListOne64:$Vt, SubRegIdx),
H A DAArch64RegisterInfo.cpp1235 unsigned SubRegIdx = Use.getOperand(OpIdx).getSubReg(); in getRegAllocationHints() local
1236 if (IsMulZPR && (getSubReg(Reg, SubRegIdx) - AArch64::Z0) % UseOps != in getRegAllocationHints()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp329 const unsigned *SubRegIdx, in copyPhysSubRegs() argument
334 Register SubDest = TRI->getSubReg(DestReg, SubRegIdx[Idx]); in copyPhysSubRegs()
335 Register SubSrc = TRI->getSubReg(SrcReg, SubRegIdx[Idx]); in copyPhysSubRegs()
392 const unsigned SubRegIdx[] = {VE::sub_vm_even, VE::sub_vm_odd}; in copyPhysReg() local
395 NumSubRegs, SubRegIdx, &getRegisterInfo()); in copyPhysReg()
398 const unsigned SubRegIdx[] = {VE::sub_even, VE::sub_odd}; in copyPhysReg() local
401 NumSubRegs, SubRegIdx, &getRegisterInfo()); in copyPhysReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupBWInsts.cpp188 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg); in getSuperRegDestIfDead() local
194 if (SubRegIdx == X86::sub_8bit_hi) in getSuperRegDestIfDead()
H A DX86ISelDAGToDAG.cpp1736 unsigned SubRegIdx = N->getConstantOperandVal(2); in PostprocessISelDAG() local
1737 if (SubRegIdx != X86::sub_xmm && SubRegIdx != X86::sub_ymm) in PostprocessISelDAG()
6195 unsigned SubRegIdx; in Select() local
6211 SubRegIdx = 0; in Select()
6219 SubRegIdx = 0; in Select()
6228 SubRegIdx = X86::sub_8bit; in Select()
6234 SubRegIdx = X86::sub_16bit; in Select()
6240 SubRegIdx = X86::sub_32bit; in Select()
6251 if (SubRegIdx != 0) { in Select()
6253 CurDAG->getTargetExtractSubreg(SubRegIdx, dl, SubRegVT, Shift); in Select()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DGIMatchTableExecutorImpl.h1160 uint16_t SubRegIdx = readU16(); in executeMatchTable() local
1163 0, SubRegIdx); in executeMatchTable()
1167 << OpIdx << ", " << SubRegIdx << ")\n"); in executeMatchTable()
1344 uint16_t SubRegIdx = readU16(); in executeMatchTable() local
1348 MI->getOperand(MI->getNumOperands() - 1).setSubReg(SubRegIdx); in executeMatchTable()
1353 << RenderOpID << ", " << SubRegIdx << ")\n"); in executeMatchTable()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp419 auto [SubRegIdx, SubReg] = SubRegQueue.front(); in computeSecondarySubRegs()
436 assert(getSubRegIndex(SubReg) == SubRegIdx && "LeadingSuperRegs correct"); in computeSecondarySubRegs()
438 if (CodeGenSubRegIndex *SubRegIdx = getSubRegIndex(SubReg)) { in computeSecondarySubRegs() local
439 if (SubRegIdx->ConcatenationOf.empty()) in computeSecondarySubRegs()
440 Parts.push_back(SubRegIdx); in computeSecondarySubRegs()
442 append_range(Parts, SubRegIdx->ConcatenationOf); in computeSecondarySubRegs()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/GlobalISel/
H A DGlobalISelMatchTable.cpp2029 const bool NeedsFlags = (SubRegIdx || IsDef); in emitRenderOpcodes()
2030 if (SubRegIdx) { in emitRenderOpcodes()
2058 if (SubRegIdx) in emitRenderOpcodes()
2059 Table << MatchTable::NamedValue(2, SubRegIdx->getQualifiedName()); in emitRenderOpcodes()
2093 ImmRenderer::emitAddImm(Table, Rule, InsnID, SubRegIdx->EnumValue, in emitRenderOpcodes()
H A DGlobalISelMatchTable.h2135 const CodeGenSubRegIndex *SubRegIdx; variable
2144 SubRegIdx(SubReg), IsDef(IsDef), IsDead(IsDead) {} in OperandRenderer()
2185 const CodeGenSubRegIndex *SubRegIdx; variable
2189 : OperandRenderer(OR_SubRegIndex), InsnID(InsnID), SubRegIdx(SRI) {} in SubRegIndexRenderer()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp2138 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32); in ExtendToInt64() local
2143 SubRegIdx), 0); in ExtendToInt64()
2152 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32); in TruncateToInt32() local
2154 MVT::i32, V, SubRegIdx), 0); in TruncateToInt32()
3222 SDValue SubRegIdx = in addExtOrTrunc() local
3225 ImDef, NatWidthRes, SubRegIdx), 0); in addExtOrTrunc()
3232 SDValue SubRegIdx = in addExtOrTrunc() local
3235 NatWidthRes, SubRegIdx), 0); in addExtOrTrunc()
5408 SDValue SubRegIdx = CurDAG->getTargetConstant(SubReg, dl, MVT::i32); in Select() local
5411 CR6Reg, SubRegIdx, BCDOp.getValue(1)), in Select()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h711 unsigned SubRegIdx) const { in getSubRegisterClass() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVLegalizerInfo.cpp1199 unsigned SubRegIdx, RemIdx; in legalizeInsertSubvector() local
1200 std::tie(SubRegIdx, RemIdx) = in legalizeInsertSubvector()

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