| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 205 unsigned SubReg1; in isProfitableToTransform() local
223 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1); in isProfitableToTransform()
297 unsigned Src1 = 0, SubReg1; in transformInstruction() local
322 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1); in transformInstruction()
346 SubReg1 = 0; in transformInstruction()
362 .addReg(Src1, getKillRegState(KillSrc1), SubReg1); in transformInstruction()
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| H A D | AArch64ISelLowering.cpp | 27466 SDValue SubReg1 = DAG.getTargetConstant(AArch64::subo64, DL, MVT::i32); in createGPRPairNode() local
27467 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 }; in createGPRPairNode()
27513 unsigned SubReg1 = AArch64::sube64, SubReg2 = AArch64::subo64; in ReplaceCMP_SWAP_128Results() local
27515 std::swap(SubReg1, SubReg2); in ReplaceCMP_SWAP_128Results()
27516 SDValue Lo = DAG.getTargetExtractSubreg(SubReg1, SDLoc(N), MVT::i64, in ReplaceCMP_SWAP_128Results()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrBuilder.h | 160 unsigned SubReg1, Register Reg2, bool isKill2, unsigned SubReg2) { in addRegReg() argument
161 return MIB.addReg(Reg1, getKillRegState(isKill1), SubReg1) in addRegReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelDAGToDAG.cpp | 388 SDValue SubReg1 = CurDAG->getTargetConstant(CSKY::sub32_32, dl, MVT::i32); in createGPRPairNode() local
389 const SDValue Ops[] = {RegClass, V0, SubReg0, V1, SubReg1}; in createGPRPairNode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1849 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32); in createGPRPairNode() local
1850 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode()
1860 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createSRegPairNode() local
1861 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createSRegPairNode()
1871 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); in createDRegPairNode() local
1872 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createDRegPairNode()
1882 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); in createQRegPairNode() local
1883 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createQRegPairNode()
1894 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createQuadSRegsNode() local
1897 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadSRegsNode()
[all …]
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| H A D | ARMISelLowering.cpp | 10525 SDValue SubReg1 = DAG.getTargetConstant(ARM::gsub_1, dl, MVT::i32); in createGPRPairNode2xi32() local
10526 const SDValue Ops[] = {RegClass, V0, SubReg0, V1, SubReg1}; in createGPRPairNode2xi32()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 203 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg(); in commuteInstructionImpl() local
246 SubReg0 = SubReg1; in commuteInstructionImpl()
266 CommutedMI->getOperand(Idx2).setSubReg(SubReg1); in commuteInstructionImpl()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 685 SDValue RC, SubReg0, SubReg1; in Select() local
690 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32); in Select()
694 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in Select()
699 N->getOperand(1), SubReg1 }; in Select()
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| H A D | SIFoldOperands.cpp | 1016 unsigned SubReg1 = Defs[I + 1].second; in isRegSeqSplat() local
1021 TRI->getChannelFromSubReg(SubReg1)) in isRegSeqSplat()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1159 unsigned SubReg1 = MI.getOperand(1).getSubReg(); in commuteInstructionImpl() local
1170 assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch"); in commuteInstructionImpl()
1202 MI.getOperand(2).setSubReg(SubReg1); in commuteInstructionImpl()
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