| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 204 unsigned SubReg0; in isProfitableToTransform() local
210 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0); in isProfitableToTransform()
296 unsigned Src0 = 0, SubReg0; in transformInstruction() local
303 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0); in transformInstruction()
340 SubReg0 = 0; in transformInstruction()
361 .addReg(Src0, getKillRegState(KillSrc0), SubReg0) in transformInstruction()
|
| H A D | AArch64ISelLowering.cpp | 27465 SDValue SubReg0 = DAG.getTargetConstant(AArch64::sube64, DL, MVT::i32); in createGPRPairNode() local
27467 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 }; in createGPRPairNode()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelDAGToDAG.cpp | 387 SDValue SubReg0 = CurDAG->getTargetConstant(CSKY::sub32_0, dl, MVT::i32); in createGPRPairNode() local
389 const SDValue Ops[] = {RegClass, V0, SubReg0, V1, SubReg1}; in createGPRPairNode()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1848 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32); in createGPRPairNode() local
1850 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode()
1859 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32); in createSRegPairNode() local
1861 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createSRegPairNode()
1870 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32); in createDRegPairNode() local
1872 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createDRegPairNode()
1881 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32); in createQRegPairNode() local
1883 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createQRegPairNode()
1893 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32); in createQuadSRegsNode() local
1897 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadSRegsNode()
[all …]
|
| H A D | ARMISelLowering.cpp | 10524 SDValue SubReg0 = DAG.getTargetConstant(ARM::gsub_0, dl, MVT::i32); in createGPRPairNode2xi32() local
10526 const SDValue Ops[] = {RegClass, V0, SubReg0, V1, SubReg1}; in createGPRPairNode2xi32()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 202 unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0; in commuteInstructionImpl() local
241 SubReg0 = SubReg2; in commuteInstructionImpl()
246 SubReg0 = SubReg1; in commuteInstructionImpl()
260 CommutedMI->getOperand(0).setSubReg(SubReg0); in commuteInstructionImpl()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 685 SDValue RC, SubReg0, SubReg1; in Select() local
689 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32); in Select()
693 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); in Select()
698 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0, in Select()
|
| H A D | SIFoldOperands.cpp | 1015 unsigned SubReg0 = Defs[I].second; in isRegSeqSplat() local
1020 if (TRI->getChannelFromSubReg(SubReg0) + 1 != in isRegSeqSplat()
|