| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterBank.cpp | 37 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
39 if (!RC.hasSubClassEq(&SubRC)) in verify()
44 assert(RBI.getMaximumSize(getID()) >= TRI.getRegSizeInBits(SubRC) && in verify()
46 assert(covers(SubRC) && "Not all subclasses are covered"); in verify()
48 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); verify() local
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| H A D | TargetRegisterInfo.cpp | 198 const TargetRegisterClass *SubRC = getRegClass(It.getID()); in getAllocatableClass() local
199 if (SubRC->isAllocatable()) in getAllocatableClass()
200 return SubRC; in getAllocatableClass()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.cpp | 1019 CodeGenRegisterClass &SubRC = *I2; in computeSubClasses() local
1020 if (RC.SubClasses.test(SubRC.EnumValue)) in computeSubClasses()
1022 if (!testSubClass(&RC, &SubRC)) in computeSubClasses()
1026 RC.SubClasses |= SubRC.SubClasses; in computeSubClasses()
2326 CodeGenRegisterClass *SubRC = getOrCreateSubClass( in inferSubClassWithSubReg() local
2328 RC->setSubClassWithSubReg(&SubIdx, SubRC); in inferSubClassWithSubReg()
2371 CodeGenRegisterClass &SubRC = *I; in inferMatchingSuperRegClass() local
2372 if (SubRC.Artificial) in inferMatchingSuperRegClass()
2375 if (!TopoSigs.anyCommon(SubRC.getTopoSigs())) in inferMatchingSuperRegClass()
2379 for (const CodeGenRegister *R : SubRC.getMembers()) { in inferMatchingSuperRegClass()
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| H A D | CodeGenRegisters.h | 426 CodeGenRegisterClass *SubRC) { in setSubClassWithSubReg() argument
427 SubClassWithSubReg[SubIdx] = SubRC; in setSubClassWithSubReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 151 if (const TargetRegisterClass *SubRC = in getRegOpRC() local
153 RC = SubRC; in getRegOpRC()
1060 if (const TargetRegisterClass *SubRC = in foldOperand() local
1062 RC = SubRC; in foldOperand()
1943 if (const auto *SubRC = TRI->getSubRegisterClass(CopyInRC, AGPRRegMask)) in tryFoldPhiAGPR() local
1944 CopyInRC = SubRC; in tryFoldPhiAGPR()
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| H A D | SIRegisterInfo.h | 262 /// subregister exists with class \p SubRC with subregister index \p
267 const TargetRegisterClass *SubRC,
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| H A D | AMDGPUInstructionSelector.h | 85 const TargetRegisterClass &SubRC,
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| H A D | SIInstrInfo.h | 112 const TargetRegisterClass *SubRC) const;
116 unsigned SubIdx, const TargetRegisterClass *SubRC) const;
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| H A D | SIInstrInfo.cpp | 4741 const TargetRegisterClass *SubRC = in verifyInstruction() local
4743 RC = RI.getCompatibleSubRegClass(RC, SubRC, MO.getSubReg()); in verifyInstruction()
4745 RC = SubRC; in verifyInstruction()
5654 unsigned SubIdx, const TargetRegisterClass *SubRC) const { in buildExtractSubReg()
5657 Register SubReg = MRI.createVirtualRegister(SubRC); in buildExtractSubReg()
5668 unsigned SubIdx, const TargetRegisterClass *SubRC) const { in buildExtractSubRegOrImm()
5679 SubIdx, SubRC); in buildExtractSubRegOrImm()
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| H A D | SIRegisterInfo.cpp | 2908 const TargetRegisterClass *SubRC, in getCompatibleSubRegClass() argument
2912 getMatchingSuperRegClass(SuperRC, SubRC, SubIdx); in getCompatibleSubRegClass()
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| H A D | AMDGPUInstructionSelector.cpp | 244 const TargetRegisterClass &SubRC, in getSubOperand64() argument
249 Register DstReg = MRI->createVirtualRegister(&SubRC); in getSubOperand64()
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| H A D | SIISelLowering.cpp | 5167 const TargetRegisterClass *SubRC = in EmitInstrWithCustomInserter() local
5170 MII, MRI, Src2, Src2RC, AMDGPU::sub0, SubRC); in EmitInstrWithCustomInserter()
5172 MII, MRI, Src2, Src2RC, AMDGPU::sub1, SubRC); in EmitInstrWithCustomInserter()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CompressInstEmitter.cpp | 173 const CodeGenRegisterClass &SubRC = Target.getRegisterClass(DagOpType); in validateTypes() local
174 return RC.hasSubClass(&SubRC); in validateTypes()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 128 if (const auto *SubRC = TRI.getCommonSubClass( in constrainOperandRegClass() local
130 OpRC = SubRC; in constrainOperandRegClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 7110 const TargetRegisterClass *SubRC; in genAlternativeCodeSequence() local
7114 SubRC = &AArch64::GPR32spRegClass; in genAlternativeCodeSequence()
7120 SubRC = &AArch64::GPR64spRegClass; in genAlternativeCodeSequence()
7125 Register NewVR = MRI.createVirtualRegister(SubRC); in genAlternativeCodeSequence()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 4445 const TargetRegisterClass *SubRC = &LoongArch::LSX128RegClass; in emitPseudoXVINSGR2VR() local
4463 Register ScratchSubReg1 = MRI.createVirtualRegister(SubRC); in emitPseudoXVINSGR2VR()
4464 Register ScratchSubReg2 = MRI.createVirtualRegister(SubRC); in emitPseudoXVINSGR2VR()
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