| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterBank.cpp | 37 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
39 if (!RC.hasSubClassEq(&SubRC)) in verify()
44 assert(RBI.getMaximumSize(getID()) >= TRI.getRegSizeInBits(SubRC) && in verify()
46 assert(covers(SubRC) && "Not all subclasses are covered"); in verify()
48 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); verify() local
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| H A D | TargetRegisterInfo.cpp | 197 const TargetRegisterClass *SubRC = getRegClass(It.getID()); in getAllocatableClass() local
198 if (SubRC->isAllocatable()) in getAllocatableClass()
199 return SubRC; in getAllocatableClass()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.cpp | 943 CodeGenRegisterClass &SubRC = *I2; in computeSubClasses() local
944 if (RC.SubClasses.test(SubRC.EnumValue)) in computeSubClasses()
946 if (!testSubClass(&RC, &SubRC)) in computeSubClasses()
950 RC.SubClasses |= SubRC.SubClasses; in computeSubClasses()
2316 CodeGenRegisterClass *SubRC = in inferSubClassWithSubReg() local
2320 RC->setSubClassWithSubReg(&SubIdx, SubRC); in inferSubClassWithSubReg()
2371 CodeGenRegisterClass &SubRC = *I; in inferMatchingSuperRegClass() local
2372 if (SubRC.Artificial) in inferMatchingSuperRegClass()
2375 if (!TopoSigs.anyCommon(SubRC.getRegsWithSuperRegsTopoSigs())) in inferMatchingSuperRegClass()
2380 auto SubI = SubRC.getMembers().begin(), SubE = SubRC.getMembers().end(); in inferMatchingSuperRegClass()
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| H A D | CodeGenRegisters.h | 434 CodeGenRegisterClass *SubRC) { in setSubClassWithSubReg() argument
435 SubClassWithSubReg[SubIdx] = SubRC; in setSubClassWithSubReg()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CompressInstEmitter.cpp | 178 const CodeGenRegisterClass &SubRC = Target.getRegisterClass(DagOpType); in validateTypes() local
179 return RC.hasSubClass(&SubRC); in validateTypes()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 308 if (const TargetRegisterClass *SubRC = in getRegOpRC() local
310 RC = SubRC; in getRegOpRC()
1423 if (const TargetRegisterClass *SubRC = in foldOperand() local
1425 RC = SubRC; in foldOperand()
2489 if (const auto *SubRC = TRI->getSubRegisterClass(CopyInRC, AGPRRegMask)) in tryFoldPhiAGPR() local
2490 CopyInRC = SubRC; in tryFoldPhiAGPR()
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| H A D | SIRegisterInfo.h | 302 const TargetRegisterClass *SubRC,
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| H A D | AMDGPUInstructionSelector.h | 85 const TargetRegisterClass &SubRC,
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| H A D | SIInstrInfo.h | 114 const TargetRegisterClass *SubRC) const;
118 unsigned SubIdx, const TargetRegisterClass *SubRC) const;
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| H A D | SIInstrInfo.cpp | 4914 if (const TargetRegisterClass *SubRC = in verifyInstruction() local
4916 RC = RI.getCompatibleSubRegClass(RC, SubRC, MO.getSubReg()); in verifyInstruction()
4918 RC = SubRC; in verifyInstruction()
5903 unsigned SubIdx, const TargetRegisterClass *SubRC) const { in buildExtractSubReg()
5909 Register SubReg = MRI.createVirtualRegister(SubRC); in buildExtractSubReg()
5920 unsigned SubIdx, const TargetRegisterClass *SubRC) const { in buildExtractSubRegOrImm()
5931 SubIdx, SubRC); in buildExtractSubRegOrImm()
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| H A D | SIRegisterInfo.cpp | 3630 const TargetRegisterClass *SubRC, in getCompatibleSubRegClass() argument
3634 getMatchingSuperRegClass(SuperRC, SubRC, SubIdx); in getCompatibleSubRegClass()
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| H A D | AMDGPUInstructionSelector.cpp | 342 const TargetRegisterClass &SubRC, in getSubOperand64() argument
347 Register DstReg = MRI->createVirtualRegister(&SubRC); in getSubOperand64()
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| H A D | SIISelLowering.cpp | 5507 const TargetRegisterClass *SubRC = in EmitInstrWithCustomInserter() local
5510 MII, MRI, Src2, Src2RC, AMDGPU::sub0, SubRC); in EmitInstrWithCustomInserter()
5512 MII, MRI, Src2, Src2RC, AMDGPU::sub1, SubRC); in EmitInstrWithCustomInserter()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 128 if (const auto *SubRC = TRI.getCommonSubClass( in constrainOperandRegClass() local
130 OpRC = SubRC; in constrainOperandRegClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 7949 const TargetRegisterClass *SubRC; in genAlternativeCodeSequence() local
7953 SubRC = &AArch64::GPR32spRegClass; in genAlternativeCodeSequence()
7959 SubRC = &AArch64::GPR64spRegClass; in genAlternativeCodeSequence()
7964 Register NewVR = MRI.createVirtualRegister(SubRC); in genAlternativeCodeSequence()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 6024 const TargetRegisterClass *SubRC = &LoongArch::LSX128RegClass; in emitPseudoXVINSGR2VR() local
6042 Register ScratchSubReg1 = MRI.createVirtualRegister(SubRC); in emitPseudoXVINSGR2VR()
6043 Register ScratchSubReg2 = MRI.createVirtualRegister(SubRC); in emitPseudoXVINSGR2VR()
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