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Searched refs:SubOp (Results 1 – 16 of 16) sorted by relevance

/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenInstAlias.cpp234 for (unsigned SubOp = 0; SubOp != NumSubOps; ++SubOp) { in CodeGenInstAlias() local
235 const Record *SubRec = cast<DefInit>(MIOI->getArg(SubOp))->getDef(); in CodeGenInstAlias()
241 MIOI->getArgName(SubOp)->getAsUnquotedString(), in CodeGenInstAlias()
243 ResultInstOperandIndex.emplace_back(OpIdx, SubOp); in CodeGenInstAlias()
254 for (unsigned SubOp = 0; SubOp != NumSubOps; ++SubOp) { in CodeGenInstAlias() local
257 const Record *SubRec = cast<DefInit>(MIOI->getArg(SubOp))->getDef(); in CodeGenInstAlias()
261 ResultInstOperandIndex.emplace_back(OpIdx, SubOp); in CodeGenInstAlias()
268 (SubOp == 0 ? InstOpRec->getName() : SubRec->getName())); in CodeGenInstAlias()
H A DCodeGenInstruction.cpp249 if (auto SubOp = findSubOperandAlias(OpName)) { in ParseOperandName() local
258 return *SubOp; in ParseOperandName()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DCompressInstEmitter.cpp237 for (unsigned SubOp = 0; SubOp != Opnd.MINumOperands; ++SubOp, ++OpNo) { in addDagOperandMapping() local
241 OpndRec = cast<DefInit>(Opnd.MIOperandInfo->getArg(SubOp))->getDef(); in addDagOperandMapping()
408 for (unsigned SubOp = 0; SubOp != Operand.MINumOperands; ++SubOp, ++OpNo) { in createInstOperandMapping() local
761 for (unsigned SubOp = 0; SubOp != SourceOperand.MINumOperands; ++SubOp) { in emitCompressInstEmitter() local
793 for (unsigned SubOp = 0; SubOp != DestOperand.MINumOperands; ++SubOp) { in emitCompressInstEmitter() local
798 cast<DefInit>(DestOperand.MIOperandInfo->getArg(SubOp))->getDef(); in emitCompressInstEmitter()
H A DCodeEmitterGen.cpp126 if (auto SubOp = CGI.Operands.findSubOperandAlias(VarName)) { in addCodeToMergeInOperand() local
127 OpIdx = CGI.Operands[SubOp->first].MIOperandNo + SubOp->second; in addCodeToMergeInOperand()
/freebsd/sys/contrib/dev/acpica/compiler/
H A Daslerror.c1515 ACPI_PARSE_OBJECT *SubOp, in AslDualParseOpError() argument
1529 if (SubOp) in AslDualParseOpError()
1531 AslInitEnode (&SubEnode, Level, SubMsgId, SubOp->Asl.LineNumber, in AslDualParseOpError()
1532 SubOp->Asl.LogicalLineNumber, SubOp->Asl.LogicalByteOffset, in AslDualParseOpError()
1533 SubOp->Asl.Column, SubOp->Asl.Filename, SubMsg, in AslDualParseOpError()
/freebsd/contrib/llvm-project/llvm/lib/TableGen/
H A DSetTheory.cpp47 struct SubOp : public SetTheory::Operator { struct
259 addOperator("sub", std::make_unique<SubOp>()); in SetTheory()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineSelect.cpp2087 Instruction *AddOp = nullptr, *SubOp = nullptr; in foldAddSubSelect() local
2093 SubOp = TI; in foldAddSubSelect()
2099 SubOp = FI; in foldAddSubSelect()
2104 if (SubOp->getOperand(0) == AddOp->getOperand(0)) { in foldAddSubSelect()
2106 } else if (SubOp->getOperand(0) == AddOp->getOperand(1)) { in foldAddSubSelect()
2115 NegVal = Builder.CreateFNeg(SubOp->getOperand(1)); in foldAddSubSelect()
2118 Flags &= SubOp->getFastMathFlags(); in foldAddSubSelect()
2122 NegVal = Builder.CreateNeg(SubOp->getOperand(1)); in foldAddSubSelect()
2134 BinaryOperator::CreateFAdd(SubOp->getOperand(0), NewSel); in foldAddSubSelect()
2137 Flags &= SubOp->getFastMathFlags(); in foldAddSubSelect()
[all …]
/freebsd/contrib/llvm-project/clang/lib/CIR/Lowering/DirectToLLVM/
H A DLowerToLLVM.cpp487 auto res = rewriter.create<mlir::LLVM::SubOp>(op.getLoc(), clz, one); in matchAndRewrite()
786 const auto sub = dyn_cast<mlir::LLVM::SubOp>(indexOp); in matchAndRewrite()
802 index = rewriter.create<mlir::LLVM::SubOp>( in matchAndRewrite()
1411 rewriter.replaceOpWithNewOp<mlir::LLVM::SubOp>(op, adaptor.getInput(), in matchAndRewrite()
1424 rewriter.replaceOpWithNewOp<mlir::LLVM::SubOp>( in matchAndRewrite()
1577 rewriter.replaceOpWithNewOp<mlir::LLVM::SubOp>(op, llvmTy, lhs, rhs, in matchAndRewrite()
2479 newReal = rewriter.create<mlir::LLVM::SubOp>(loc, complexElemTy, lhsReal, in matchAndRewrite()
2481 newImag = rewriter.create<mlir::LLVM::SubOp>(loc, complexElemTy, lhsImag, in matchAndRewrite()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp1226 unsigned SubOp = AMDGPU::V_SUB_CO_U32_e32; in SelectDS1Addr1Offset() local
1228 SubOp = AMDGPU::V_SUB_U32_e64; in SelectDS1Addr1Offset()
1234 CurDAG->getMachineNode(SubOp, DL, MVT::i32, Opnds); in SelectDS1Addr1Offset()
1411 unsigned SubOp = AMDGPU::V_SUB_CO_U32_e32; in SelectDSReadWrite2() local
1413 SubOp = AMDGPU::V_SUB_U32_e64; in SelectDSReadWrite2()
1419 SubOp, DL, MVT::getIntegerVT(Size * 8), Opnds); in SelectDSReadWrite2()
H A DSIInstrInfo.cpp8128 unsigned SubOp = ST.hasAddNoCarry() ? in lowerScalarAbs() local
8131 BuildMI(MBB, MII, DL, get(SubOp), TmpReg) in lowerScalarAbs()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp4203 unsigned SubOp; in expandDivRem() local
4208 SubOp = Mips::DSUB; in expandDivRem()
4212 SubOp = Mips::SUB; in expandDivRem()
4248 TOut.emitRRR(SubOp, RdReg, ZeroReg, RsReg, IDLoc, STI); in expandDivRem()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2051 SDValue SubOp = Node->getOperand(i); in LowerCONCAT_VECTORS() local
2052 EVT VVT = SubOp.getNode()->getValueType(0); in LowerCONCAT_VECTORS()
2056 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp, in LowerCONCAT_VECTORS()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp3418 SDValue SubOp = Op.getOperand(i); in SimplifyDemandedVectorElts() local
3421 if (SimplifyDemandedVectorElts(SubOp, SubElts, SubUndef, SubZero, TLO, in SimplifyDemandedVectorElts()
3433 SDValue SubOp = Op.getOperand(i); in SimplifyDemandedVectorElts() local
3436 SubOp, SubElts, TLO.DAG, Depth + 1); in SimplifyDemandedVectorElts()
3437 DemandedSubOps.push_back(NewSubOp ? NewSubOp : SubOp); in SimplifyDemandedVectorElts()
H A DLegalizeDAG.cpp1562 SDValue SubOp = Node->getOperand(I); in ExpandConcatVectors() local
1565 SubOp, in ExpandConcatVectors()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp58359 for (SDValue SubOp : SubOps) in combineConcatVectorOps() local
58360 Subs.push_back(SubOp.getOperand(I)); in combineConcatVectorOps()
58382 if (isa<LoadSDNode>(BC0) && all_of(SubOps, [&](SDValue SubOp) { in combineConcatVectorOps() argument
58383 return BC0 == peekThroughBitcasts(SubOp.getOperand(Op)); in combineConcatVectorOps()
58401 for (SDValue SubOp : SubOps) { in combineConcatVectorOps() local
58402 SDValue BC = peekThroughBitcasts(SubOp.getOperand(I)); in combineConcatVectorOps()
58405 Subs.push_back(SubOp.getOperand(I)); in combineConcatVectorOps()
58417 for (SDValue SubOp : Ops) in combineConcatVectorOps() local
58418 SubOps.push_back(peekThroughBitcasts(SubOp.getOperand(0))); in combineConcatVectorOps()
59354 if (all_of(SubVectorOps, [](SDValue SubOp) { in combineINSERT_SUBVECTOR() argument
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp9207 SDValue SubOp = DAG.getNode(ISD::SUB, DL, VT, RegV, ConstVal); in lowerSELECT() local
9210 DL, VT, SubOp, CondV); in lowerSELECT()