| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | DetectDeadLanes.cpp | 158 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes() local
159 return TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
162 unsigned SubIdx = MI.getOperand(3).getImm(); in transferUsedLanes() local
164 TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
173 MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx); in transferUsedLanes()
182 unsigned SubIdx = MI.getOperand(2).getImm(); in transferUsedLanes() local
183 return TRI->composeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
232 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes() local
233 DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes); in transferDefinedLanes()
234 DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx); in transferDefinedLanes()
[all …]
|
| H A D | ExpandPostRAPseudos.cpp | 69 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
71 assert(SubIdx != 0 && "Invalid index for insert_subreg"); in LowerSubregToReg()
72 Register DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
|
| H A D | TargetRegisterInfo.cpp | 109 unsigned SubIdx, const MachineRegisterInfo *MRI) { in printReg() argument
110 return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) { in printReg()
130 if (SubIdx) { in printReg()
132 OS << ':' << TRI->getSubRegIndexName(SubIdx); in printReg()
134 OS << ":sub(" << SubIdx << ')'; in printReg()
|
| H A D | PeepholeOptimizer.cpp | 507 unsigned SubIdx; in INITIALIZE_PASS_DEPENDENCY() local
508 if (!TII->isCoalescableExtInstr(MI, SrcReg, DstReg, SubIdx)) in INITIALIZE_PASS_DEPENDENCY()
521 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
531 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr; in INITIALIZE_PASS_DEPENDENCY()
557 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
650 .addReg(DstReg, 0, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
1987 if (RegSeqInput.SubIdx == DefSubReg) in getNextSourceFromRegSequence()
2024 if (InsertedReg.SubIdx == DefSubReg) { in getNextSourceFromInsertSubreg()
2043 TRI->getSubRegIndexLaneMask(InsertedReg.SubIdx)).none()) in getNextSourceFromInsertSubreg()
2076 ExtractSubregInputReg.SubIdx); in getNextSourceFromExtractSubreg()
|
| H A D | RegisterCoalescer.cpp | 309 void updateRegDefsUses(Register SrcReg, Register DstReg, unsigned SubIdx);
1817 unsigned SubIdx) { in updateRegDefsUses() argument
1854 if (DstInt && !Reads && SubIdx && !UseMI->isDebugInstr()) in updateRegDefsUses()
1864 if (SubIdx && MO.isDef()) in updateRegDefsUses()
1870 unsigned SubUseIdx = TRI->composeSubRegIndices(SubIdx, MO.getSubReg()); in updateRegDefsUses()
1875 LaneBitmask UsedLanes = TRI->getSubRegIndexLaneMask(SubIdx); in updateRegDefsUses()
1895 MO.substVirtReg(DstReg, SubIdx, *TRI); in updateRegDefsUses()
2415 const unsigned SubIdx; member in __anonf9586a8a0311::JoinVals
2589 JoinVals(LiveRange &LR, Register Reg, unsigned SubIdx, LaneBitmask LaneMask, in JoinVals() argument
2593 : LR(LR), Reg(Reg), SubIdx(SubIdx), LaneMask(LaneMask), in JoinVals()
[all …]
|
| H A D | MachineOperand.cpp | 83 void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx, in substVirtReg() argument
86 if (SubIdx && getSubReg()) in substVirtReg()
87 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg()
89 if (SubIdx) in substVirtReg()
90 setSubReg(SubIdx); in substVirtReg()
|
| H A D | TargetInstrInfo.cpp | 389 unsigned SubIdx, unsigned &Size, in getStackSlotRange() argument
393 if (!SubIdx) { in getStackSlotRange()
398 unsigned BitSize = TRI->getSubRegIdxSize(SubIdx); in getStackSlotRange()
403 int BitOffset = TRI->getSubRegIdxOffset(SubIdx); in getStackSlotRange()
420 Register DestReg, unsigned SubIdx, in reMaterialize() argument
424 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI); in reMaterialize()
1699 InputReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getExtractSubregInputs()
1727 InsertedReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getInsertSubregInputs()
|
| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.cpp | 139 CodeGenSubRegIndex *SubIdx = *I; in computeConcatTransitiveClosure() local
140 SubIdx->computeConcatTransitiveClosure(); in computeConcatTransitiveClosure()
142 for (CodeGenSubRegIndex *SRI : SubIdx->ConcatenationOf) in computeConcatTransitiveClosure()
146 if (SubIdx->ConcatenationOf.empty()) { in computeConcatTransitiveClosure()
150 I = ConcatenationOf.insert(I, SubIdx->ConcatenationOf.begin(), in computeConcatTransitiveClosure()
151 SubIdx->ConcatenationOf.end()); in computeConcatTransitiveClosure()
152 I += SubIdx->ConcatenationOf.size(); in computeConcatTransitiveClosure()
547 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SubReg.second); in computeSecondarySubRegs() local
548 if (!SubIdx) in computeSecondarySubRegs()
552 NewIdx->addComposite(SubReg.first, SubIdx, RegBank.getHwModes()); in computeSecondarySubRegs()
[all …]
|
| H A D | CodeGenRegisters.h | 407 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg() argument
408 return SubClassWithSubReg.lookup(SubIdx); in getSubClassWithSubReg()
423 const CodeGenSubRegIndex *SubIdx) const;
425 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, in setSubClassWithSubReg() argument
427 SubClassWithSubReg[SubIdx] = SubRC; in setSubClassWithSubReg()
432 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
436 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, in addSuperRegClass() argument
438 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
|
| H A D | CodeGenTarget.cpp | 181 const CodeGenSubRegIndex *SubIdx, bool MustBeAllocatable) const { in getSuperRegForSubReg() argument
189 CodeGenRegisterClass *SubClassWithSubReg = RC.getSubClassWithSubReg(SubIdx); in getSuperRegForSubReg()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 388 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName() argument
389 assert(SubIdx && SubIdx < getNumSubRegIndices() && in getSubRegIndexName()
391 return SubRegIndexNames[SubIdx-1]; in getSubRegIndexName()
408 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask() argument
409 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); in getSubRegIndexLaneMask()
410 return SubRegIndexLaneMasks[SubIdx]; in getSubRegIndexLaneMask()
640 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg() argument
642 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); in getMatchingSuperReg()
1388 unsigned SubIdx = 0,
|
| H A D | TargetInstrInfo.h | 265 Register &DstReg, unsigned &SubIdx) const { in isCoalescableExtInstr() argument
366 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
415 unsigned SubIdx, const MachineInstr &Orig,
522 unsigned SubIdx; member
525 unsigned SubIdx = 0)
526 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
|
| H A D | LiveRangeEdit.h | 215 bool Late = false, unsigned SubIdx = 0,
|
| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | GlobalISelEmitter.cpp | 1311 CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(ChildRec); in importExplicitUseRenderer() local
1312 DstMIBuilder.addRenderer<ImmRenderer>(SubIdx->EnumValue); in importExplicitUseRenderer()
1445 auto SubIdx = inferSubRegIndexForNode(Dst.getChild(1)); in createAndImportSubInstructionRenderer() local
1446 if (!SubIdx) in createAndImportSubInstructionRenderer()
1450 (*SuperClass)->getMatchingSubClassWithSubRegs(CGRegs, *SubIdx); in createAndImportSubInstructionRenderer()
1490 auto SubIdx = inferSubRegIndexForNode(SubRegChild); in createAndImportSubInstructionRenderer() local
1491 if (!SubIdx) in createAndImportSubInstructionRenderer()
1495 (*SuperClass)->getMatchingSubClassWithSubRegs(CGRegs, *SubIdx); in createAndImportSubInstructionRenderer()
1587 CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef()); in importExplicitUseRenderers() local
1605 DstMIBuilder.addRenderer<TempRegRenderer>(TempRegID, false, SubIdx); in importExplicitUseRenderers()
[all …]
|
| H A D | RegisterBankEmitter.cpp | 203 for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) { in visitRegisterBankClasses() local
205 PossibleSubclass.getSuperRegClasses(&SubIdx, BV); in visitRegisterBankClasses()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TileConfig.cpp | 183 unsigned SubIdx = IsRow ? X86::sub_8bit : X86::sub_16bit; in INITIALIZE_PASS_DEPENDENCY() local
186 SubIdx = 0; in INITIALIZE_PASS_DEPENDENCY()
195 .addReg(R, 0, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
|
| H A D | X86InstructionSelector.cpp | |
| H A D | X86LegalizerInfo.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ThumbRegisterInfo.cpp | 64 unsigned SubIdx, int Val, in emitThumb1LoadConstPool() argument
76 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
84 unsigned SubIdx, int Val, in emitThumb2LoadConstPool() argument
95 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
105 const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, in emitLoadConstPool() argument
112 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
115 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
|
| H A D | ThumbRegisterInfo.h | 41 const DebugLoc &dl, Register DestReg, unsigned SubIdx,
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 218 unsigned SubIdx = X86::NoSubRegister; in getSubRegIndex() local
220 SubIdx = X86::sub_32bit; in getSubRegIndex()
222 SubIdx = X86::sub_16bit; in getSubRegIndex()
224 SubIdx = X86::sub_8bit; in getSubRegIndex()
227 return SubIdx; in getSubRegIndex()
826 unsigned SubIdx; in selectTruncOrPtrToInt() local
829 SubIdx = X86::NoSubRegister; in selectTruncOrPtrToInt()
831 SubIdx = X86::sub_32bit; in selectTruncOrPtrToInt()
833 SubIdx = X86::sub_16bit; in selectTruncOrPtrToInt()
835 SubIdx = X86::sub_8bit; in selectTruncOrPtrToInt()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 476 Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx, in ConstrainForSubReg() argument
479 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
492 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx); in ConstrainForSubReg()
525 unsigned SubIdx = Node->getConstantOperandVal(1); in EmitSubregNode() local
544 SubIdx == DefSubIdx && in EmitSubregNode()
560 Reg = ConstrainForSubReg(Reg, SubIdx, in EmitSubregNode()
572 CopyMI.addReg(Reg, 0, SubIdx); in EmitSubregNode()
574 CopyMI.addReg(TRI->getSubReg(Reg, SubIdx)); in EmitSubregNode()
581 unsigned SubIdx = N2->getAsZExtVal(); in EmitSubregNode() local
599 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); in EmitSubregNode()
[all …]
|
| H A D | InstrEmitter.h | 85 Register ConstrainForSubReg(Register VReg, unsigned SubIdx, MVT VT,
|
| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 108 MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg() argument
111 if (RC->contains(Super) && Reg == getSubReg(Super, SubIdx)) in getMatchingSuperReg()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVPrepareFunctions.cpp | 224 for (std::size_t SubIdx = 1; SubIdx < MatchStr.size(); ++SubIdx) in parseAnnotation() local
225 if (std::string SubStr = MatchStr[SubIdx].str(); SubStr.length()) in parseAnnotation()
|