| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | DetectDeadLanes.cpp | 158 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes() local
159 return TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
162 unsigned SubIdx = MI.getOperand(3).getImm(); in transferUsedLanes() local
164 TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
173 MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx); in transferUsedLanes()
182 unsigned SubIdx = MI.getOperand(2).getImm(); in transferUsedLanes() local
183 return TRI->composeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
232 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes() local
233 DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes); in transferDefinedLanes()
234 DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx); in transferDefinedLanes()
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| H A D | ExpandPostRAPseudos.cpp | 88 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
90 assert(SubIdx != 0 && "Invalid index for insert_subreg"); in LowerSubregToReg()
91 Register DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
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| H A D | PeepholeOptimizer.cpp | 781 unsigned SubIdx; in INITIALIZE_PASS_DEPENDENCY() local
782 if (!TII->isCoalescableExtInstr(MI, SrcReg, DstReg, SubIdx)) in INITIALIZE_PASS_DEPENDENCY()
795 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
805 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr; in INITIALIZE_PASS_DEPENDENCY()
831 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
924 .addReg(DstReg, 0, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
1977 if (RegSeqInput.SubIdx == DefSubReg) in getNextSourceFromRegSequence()
1987 LaneBitmask ThisOpRegMask = TRI->getSubRegIndexLaneMask(RegSeqInput.SubIdx); in getNextSourceFromRegSequence()
1997 TRI->reverseComposeSubRegIndices(RegSeqInput.SubIdx, DefSubReg); in getNextSourceFromRegSequence()
2040 if (InsertedReg.SubIdx == DefSubReg) { in getNextSourceFromInsertSubreg()
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| H A D | TargetRegisterInfo.cpp | 108 unsigned SubIdx, const MachineRegisterInfo *MRI) { in printReg() argument
109 return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) { in printReg()
129 if (SubIdx) { in printReg()
131 OS << ':' << TRI->getSubRegIndexName(SubIdx); in printReg()
133 OS << ":sub(" << SubIdx << ')'; in printReg()
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| H A D | RegisterCoalescer.cpp | 309 void updateRegDefsUses(Register SrcReg, Register DstReg, unsigned SubIdx);
1874 unsigned SubIdx) { in updateRegDefsUses() argument
1914 if (DstInt && !Reads && SubIdx && !UseMI->isDebugInstr()) in updateRegDefsUses()
1924 if (SubIdx && MO.isDef()) in updateRegDefsUses()
1930 unsigned SubUseIdx = TRI->composeSubRegIndices(SubIdx, MO.getSubReg()); in updateRegDefsUses()
1935 LaneBitmask UsedLanes = TRI->getSubRegIndexLaneMask(SubIdx); in updateRegDefsUses()
1955 MO.substVirtReg(DstReg, SubIdx, *TRI); in updateRegDefsUses()
2475 const unsigned SubIdx; member in __anonf9586a8a0311::JoinVals
2650 JoinVals(LiveRange &LR, Register Reg, unsigned SubIdx, LaneBitmask LaneMask, in JoinVals() argument
2654 : LR(LR), Reg(Reg), SubIdx(SubIdx), LaneMask(LaneMask), in JoinVals()
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| H A D | MachineOperand.cpp | 82 void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx, in substVirtReg() argument
85 if (SubIdx && getSubReg()) in substVirtReg()
86 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg()
88 if (SubIdx) in substVirtReg()
89 setSubReg(SubIdx); in substVirtReg()
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| H A D | TargetInstrInfo.cpp | 423 unsigned SubIdx, unsigned &Size, in getStackSlotRange() argument
427 if (!SubIdx) { in getStackSlotRange()
432 unsigned BitSize = TRI->getSubRegIdxSize(SubIdx); in getStackSlotRange()
437 int BitOffset = TRI->getSubRegIdxOffset(SubIdx); in getStackSlotRange()
454 Register DestReg, unsigned SubIdx, in reMaterialize() argument
458 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI); in reMaterialize()
2009 InputReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getExtractSubregInputs()
2037 InsertedReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getInsertSubregInputs()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.cpp | 141 CodeGenSubRegIndex *SubIdx = *I; in computeConcatTransitiveClosure() local
142 SubIdx->computeConcatTransitiveClosure(); in computeConcatTransitiveClosure()
144 for (CodeGenSubRegIndex *SRI : SubIdx->ConcatenationOf) in computeConcatTransitiveClosure()
148 if (SubIdx->ConcatenationOf.empty()) { in computeConcatTransitiveClosure()
152 I = ConcatenationOf.insert(I, SubIdx->ConcatenationOf.begin(), in computeConcatTransitiveClosure()
153 SubIdx->ConcatenationOf.end()); in computeConcatTransitiveClosure()
154 I += SubIdx->ConcatenationOf.size(); in computeConcatTransitiveClosure()
474 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SubReg); in computeSecondarySubRegs() local
475 if (!SubIdx) in computeSecondarySubRegs()
479 NewIdx->addComposite(SRI, SubIdx, RegBank.getHwModes()); in computeSecondarySubRegs()
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| H A D | CodeGenRegisters.h | 415 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg() argument
416 return SubClassWithSubReg.lookup(SubIdx); in getSubClassWithSubReg()
431 const CodeGenSubRegIndex *SubIdx) const;
433 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, in setSubClassWithSubReg() argument
435 SubClassWithSubReg[SubIdx] = SubRC; in setSubClassWithSubReg()
440 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
444 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, in addSuperRegClass() argument
446 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
449 void extendSuperRegClasses(CodeGenSubRegIndex *SubIdx);
836 const CodeGenSubRegIndex *SubIdx,
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 402 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName() argument
403 assert(SubIdx && SubIdx < getNumSubRegIndices() && in getSubRegIndexName()
405 return SubRegIndexNames[SubIdx-1]; in getSubRegIndexName()
422 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask() argument
423 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); in getSubRegIndexLaneMask()
424 return SubRegIndexLaneMasks[SubIdx]; in getSubRegIndexLaneMask()
666 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg() argument
668 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); in getMatchingSuperReg()
1415 unsigned SubIdx = 0,
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| H A D | TargetInstrInfo.h | 278 Register &DstReg, unsigned &SubIdx) const { in isCoalescableExtInstr() argument
379 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
428 unsigned SubIdx, const MachineInstr &Orig,
545 unsigned SubIdx; member
548 unsigned SubIdx = 0)
549 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
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| H A D | LiveRangeEdit.h | 213 bool Late = false, unsigned SubIdx = 0,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | |
| H A D | X86TileConfig.cpp | 242 unsigned SubIdx = IsRow ? X86::sub_8bit : X86::sub_16bit; in runOnMachineFunction() local
245 SubIdx = 0; in runOnMachineFunction()
254 .addReg(R, 0, SubIdx); in runOnMachineFunction()
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| H A D | X86LegalizerInfo.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 222 unsigned SubIdx = X86::NoSubRegister; in getSubRegIndex() local
224 SubIdx = X86::sub_32bit; in getSubRegIndex()
226 SubIdx = X86::sub_16bit; in getSubRegIndex()
228 SubIdx = X86::sub_8bit; in getSubRegIndex()
231 return SubIdx; in getSubRegIndex()
854 unsigned SubIdx; in selectTruncOrPtrToInt() local
857 SubIdx = X86::NoSubRegister; in selectTruncOrPtrToInt()
859 SubIdx = X86::sub_32bit; in selectTruncOrPtrToInt()
861 SubIdx = X86::sub_16bit; in selectTruncOrPtrToInt()
863 SubIdx = X86::sub_8bit; in selectTruncOrPtrToInt()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ThumbRegisterInfo.cpp | 62 unsigned SubIdx, int Val, in emitThumb1LoadConstPool() argument
74 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
82 unsigned SubIdx, int Val, in emitThumb2LoadConstPool() argument
93 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
103 const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, in emitLoadConstPool() argument
110 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
113 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
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| H A D | ThumbRegisterInfo.h | 41 const DebugLoc &dl, Register DestReg, unsigned SubIdx,
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| H A D | ARMBaseRegisterInfo.h | 137 const DebugLoc &dl, Register DestReg, unsigned SubIdx,
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 473 Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx, in ConstrainForSubReg() argument
476 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
489 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx); in ConstrainForSubReg()
521 unsigned SubIdx = Node->getConstantOperandVal(1); in EmitSubregNode() local
540 SubIdx == DefSubIdx && in EmitSubregNode()
556 Reg = ConstrainForSubReg(Reg, SubIdx, in EmitSubregNode()
568 CopyMI.addReg(Reg, 0, SubIdx); in EmitSubregNode()
570 CopyMI.addReg(TRI->getSubReg(Reg, SubIdx)); in EmitSubregNode()
577 unsigned SubIdx = N2->getAsZExtVal(); in EmitSubregNode() local
595 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); in EmitSubregNode()
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| H A D | InstrEmitter.h | 88 Register ConstrainForSubReg(Register VReg, unsigned SubIdx, MVT VT,
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | GlobalISelEmitter.cpp | 1618 const CodeGenSubRegIndex *SubIdx = in importExplicitUseRenderers() local
1637 DstMIBuilder.addRenderer<TempRegRenderer>(TempRegID, false, SubIdx); in importExplicitUseRenderers()
1650 RC->getMatchingSubClassWithSubRegs(CGRegs, SubIdx); in importExplicitUseRenderers()
1661 std::get<2>(*SubOperand), SubIdx); in importExplicitUseRenderers()
1665 DstMIBuilder.addRenderer<CopySubRegRenderer>(RegOperandName, SubIdx); in importExplicitUseRenderers()
1688 const CodeGenSubRegIndex *SubIdx = in importExplicitUseRenderers() local
1694 DstMIBuilder.addRenderer<SubRegIndexRenderer>(SubIdx); in importExplicitUseRenderers()
1807 const CodeGenSubRegIndex *SubIdx = inferSubRegIndexForNode(Dst.getChild(1)); in constrainOperands() local
1808 if (!SubIdx) in constrainOperands()
1818 SuperClass->getMatchingSubClassWithSubRegs(CGRegs, SubIdx); in constrainOperands()
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| H A D | RegisterBankEmitter.cpp | 207 for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) { in visitRegisterBankClasses() local
209 PossibleSubclass.getSuperRegClasses(&SubIdx, BV); in visitRegisterBankClasses()
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| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 108 MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg() argument
111 if (RC->contains(Super) && Reg == getSubReg(Super, SubIdx)) in getMatchingSuperReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVPrepareFunctions.cpp | 219 for (std::size_t SubIdx = 1; SubIdx < MatchStr.size(); ++SubIdx) in parseAnnotation() local
220 if (std::string SubStr = MatchStr[SubIdx].str(); SubStr.length()) in parseAnnotation()
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