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Searched refs:SubHi (Results 1 – 4 of 4) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBitSimplify.cpp471 unsigned SubHi = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_hi); in parseRegSequence() local
472 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence()
473 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence()
478 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence()
1658 unsigned SubHi = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_hi); in processBlock() local
1660 BitTracker::RegisterRef TH = { R, SubHi }; in processBlock()
1669 .addImm(SubHi); in processBlock()
1723 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local
1725 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI); in propagateRegCopy()
1733 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local
[all …]
H A DHexagonConstPropagation.cpp1954 unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi); in evaluate() local
1955 if (Sub1 != SubLo && Sub1 != SubHi) in evaluate()
1957 if (Sub2 != SubLo && Sub2 != SubHi) in evaluate()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DBUFInstructions.td1861 defvar SubHi = !if(!eq(vt, i32), sub1, sub2_sub3);
1864 (REG_SEQUENCE DataRC, SrcRC:$data, SubLo, SrcRC:$cmp, SubHi),
1876 (REG_SEQUENCE DataRC, SrcRC:$data, SubLo, SrcRC:$cmp, SubHi),
1890 (REG_SEQUENCE DataRC, SrcRC:$data, SubLo, SrcRC:$cmp, SubHi),
1904 (REG_SEQUENCE DataRC, SrcRC:$data, SubLo, SrcRC:$cmp, SubHi),
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp41211 if (SDValue SubHi = FindSubVector128((Imm & 0xF0) >> 4)) { in combineTargetShuffle() local
41214 SubHi = DAG.getBitcast(SubVT, SubHi); in combineTargetShuffle()
41215 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, SubLo, SubHi); in combineTargetShuffle()