Searched refs:Sub2 (Results 1 – 7 of 7) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | ExpandLargeFpConvert.cpp | 378 Value *Sub2 = Builder.CreateSub(Builder.getIntN(BitWidthNew, BitWidth - 1), in expandIToFP() local
439 ExtractT64 = Builder.CreateTrunc(Sub2, Builder.getInt64Ty()); in expandIToFP()
473 ExtractT66 = Builder.CreateTrunc(Sub2, Builder.getIntNTy(64)); in expandIToFP()
496 E0->addIncoming(Sub2, SwEpilog); in expandIToFP()
497 E0->addIncoming(Sub2, IfElse); in expandIToFP()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 1542 unsigned Sub2 = DI->getOperand(2).getImm(); in checkForImmediate() local
1544 if (Sub2 == Hexagon::isub_lo && Sub4 == Hexagon::isub_hi) in checkForImmediate()
1546 else if (Sub2 == Hexagon::isub_hi && Sub4 == Hexagon::isub_lo) in checkForImmediate()
|
| H A D | HexagonBitSimplify.cpp | 466 unsigned Sub1 = I.getOperand(2).getImm(), Sub2 = I.getOperand(4).getImm(); in parseRegSequence() local
472 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence()
473 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence()
478 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence()
|
| H A D | HexagonConstPropagation.cpp | 1951 unsigned Sub2 = MI.getOperand(4).getImm(); in evaluate() local
1957 if (Sub2 != SubLo && Sub2 != SubHi) in evaluate()
1959 assert(Sub1 != Sub2); in evaluate()
|
| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.cpp | 1479 const CodeGenSubRegIndex *Sub2) { in computeComposites() argument
1482 const RegMap &Img2 = SubRegAction.at(Sub2); in computeComposites()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 4630 auto Sub2 = B.buildMergeLikeInstr(S64, {Sub2_Lo, Sub2_Hi}); in legalizeUnsignedDIV_REM64Impl() local
4662 S64, B.buildICmp(CmpInst::ICMP_NE, S1, C6, Zero32), Sub3, Sub2); in legalizeUnsignedDIV_REM64Impl()
|
| H A D | AMDGPUISelLowering.cpp | 2153 SDValue Sub2 = DAG.getBitcast(VT, in LowerUDIVREM64() local
2182 SDValue Sel2 = DAG.getSelectCC(DL, C6, Zero, Sub3, Sub2, ISD::SETNE); in LowerUDIVREM64()
|