Searched refs:Sub2 (Results 1 – 8 of 8) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | ExpandFp.cpp | 383 Value *Sub2 = Builder.CreateSub(Builder.getIntN(BitWidthNew, BitWidth - 1), in expandIToFP() local
444 ExtractT64 = Builder.CreateTrunc(Sub2, Builder.getInt64Ty()); in expandIToFP()
478 ExtractT66 = Builder.CreateTrunc(Sub2, Builder.getIntNTy(64)); in expandIToFP()
501 E0->addIncoming(Sub2, SwEpilog); in expandIToFP()
502 E0->addIncoming(Sub2, IfElse); in expandIToFP()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 1579 unsigned Sub2 = DI->getOperand(2).getImm(); in checkForImmediate() local
1581 if (Sub2 == Hexagon::isub_lo && Sub4 == Hexagon::isub_hi) in checkForImmediate()
1583 else if (Sub2 == Hexagon::isub_hi && Sub4 == Hexagon::isub_lo) in checkForImmediate()
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| H A D | HexagonBitSimplify.cpp | 444 unsigned Sub1 = I.getOperand(2).getImm(), Sub2 = I.getOperand(4).getImm(); in parseRegSequence() local
450 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence()
451 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence()
456 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence()
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| H A D | HexagonConstPropagation.cpp | 1948 unsigned Sub2 = MI.getOperand(4).getImm(); in evaluate() local
1954 if (Sub2 != SubLo && Sub2 != SubHi) in evaluate()
1956 assert(Sub1 != Sub2); in evaluate()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 7851 GSub *Sub2 = cast<GSub>(MRI.getVRegDef(Sub1->getLHSReg())); in matchFoldAMinusC1MinusC2() local
7853 if (!MRI.hasOneNonDBGUse(Sub2->getReg(0))) in matchFoldAMinusC1MinusC2()
7857 APInt C1 = getIConstantFromReg(Sub2->getRHSReg(), MRI); in matchFoldAMinusC1MinusC2()
7864 B.buildSub(Dst, Sub2->getLHSReg(), Const); in matchFoldAMinusC1MinusC2()
7874 GSub *Sub2 = cast<GSub>(MRI.getVRegDef(Sub1->getLHSReg())); in matchFoldC1Minus2MinusC2() local
7876 if (!MRI.hasOneNonDBGUse(Sub2->getReg(0))) in matchFoldC1Minus2MinusC2()
7880 APInt C1 = getIConstantFromReg(Sub2->getLHSReg(), MRI); in matchFoldC1Minus2MinusC2()
7887 B.buildSub(Dst, Const, Sub2->getRHSReg()); in matchFoldC1Minus2MinusC2()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.cpp | 1414 const CodeGenSubRegIndex *Sub2) { in computeComposites() argument
1417 const RegMap &Img2 = SubRegAction.at(Sub2); in computeComposites()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 2210 SDValue Sub2 = DAG.getBitcast(VT, in LowerUDIVREM64() local
2239 SDValue Sel2 = DAG.getSelectCC(DL, C6, Zero, Sub3, Sub2, ISD::SETNE); in LowerUDIVREM64()
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| H A D | AMDGPULegalizerInfo.cpp | 4688 auto Sub2 = B.buildMergeLikeInstr(S64, {Sub2_Lo, Sub2_Hi}); in legalizeUnsignedDIV_REM64Impl() local
4720 S64, B.buildICmp(CmpInst::ICMP_NE, S1, C6, Zero32), Sub3, Sub2); in legalizeUnsignedDIV_REM64Impl()
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