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Searched refs:Sub1 (Results 1 – 16 of 16) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp252 SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl, MVT::i32, in tryInlineAsm() local
256 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in tryInlineAsm()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DExpandFp.cpp381 Value *Sub1 = Builder.CreateSub(Builder.getIntN(BitWidthNew, BitWidth), in expandIToFP() local
386 Sub1, Builder.getIntN(BitWidthNew, FPMantissaWidth + 1)); in expandIToFP()
391 llvm::SwitchInst *SI = Builder.CreateSwitch(Sub1, SwDefault); in expandIToFP()
460 ExtractT62 = Builder.CreateTrunc(Sub1, Builder.getIntNTy(64)); in expandIToFP()
500 E0->addIncoming(Sub1, IfThen20); in expandIToFP()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp220 SDValue Sub1 = in selectInlineAsm() local
224 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in selectInlineAsm()
/freebsd/contrib/llvm-project/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
H A DBasicValueFactory.h216 APSIntPtr Sub1(const llvm::APSInt &V) { in Sub1() function
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp971 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in SelectADD_SUB_I64() local
976 DL, MVT::i32, LHS, Sub1); in SelectADD_SUB_I64()
981 DL, MVT::i32, RHS, Sub1); in SelectADD_SUB_I64()
1014 Sub1, in SelectADD_SUB_I64()
1173 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, SL, MVT::i32); in SelectMUL_LOHI() local
1175 MVT::i32, SDValue(Mad, 0), Sub1); in SelectMUL_LOHI()
1810 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in SelectFlatOffsetImpl() local
1815 DL, MVT::i32, N0, Sub1); in SelectFlatOffsetImpl()
1832 SDValue(Add, 0), Sub0, SDValue(Addc, 0), Sub1}; in SelectFlatOffsetImpl()
H A DAMDGPUISelLowering.cpp2189 SDValue Sub1 = DAG.getBitcast(VT, in LowerUDIVREM64() local
2240 SDValue Rem = DAG.getSelectCC(DL, C3, Zero, Sel2, Sub1, ISD::SETNE); in LowerUDIVREM64()
H A DAMDGPULegalizerInfo.cpp4665 auto Sub1 = B.buildMergeLikeInstr(S64, {Sub1_Lo, Sub1_Hi}); in legalizeUnsignedDIV_REM64Impl() local
4722 Sel2, Sub1); in legalizeUnsignedDIV_REM64Impl()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCodeEmitter.cpp464 const MCInst *Sub1 = MI.getOperand(1).getInst(); in encodeSingleInstruction() local
470 unsigned SubBits1 = getBinaryCodeForInstr(*Sub1, Fixups, STI); in encodeSingleInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBitSimplify.cpp444 unsigned Sub1 = I.getOperand(2).getImm(), Sub2 = I.getOperand(4).getImm(); in parseRegSequence() local
450 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence()
451 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence()
456 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence()
H A DHexagonConstPropagation.cpp1947 unsigned Sub1 = MI.getOperand(2).getImm(); in evaluate() local
1952 if (Sub1 != SubLo && Sub1 != SubHi) in evaluate()
1956 assert(Sub1 != Sub2); in evaluate()
1957 bool LoIs1 = (Sub1 == SubLo); in evaluate()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp7850 const GSub *Sub1 = cast<GSub>(&MI); in matchFoldAMinusC1MinusC2() local
7851 GSub *Sub2 = cast<GSub>(MRI.getVRegDef(Sub1->getLHSReg())); in matchFoldAMinusC1MinusC2()
7856 APInt C2 = getIConstantFromReg(Sub1->getRHSReg(), MRI); in matchFoldAMinusC1MinusC2()
7859 Register Dst = Sub1->getReg(0); in matchFoldAMinusC1MinusC2()
7873 const GSub *Sub1 = cast<GSub>(&MI); in matchFoldC1Minus2MinusC2() local
7874 GSub *Sub2 = cast<GSub>(MRI.getVRegDef(Sub1->getLHSReg())); in matchFoldC1Minus2MinusC2()
7879 APInt C2 = getIConstantFromReg(Sub1->getRHSReg(), MRI); in matchFoldC1Minus2MinusC2()
7882 Register Dst = Sub1->getReg(0); in matchFoldC1Minus2MinusC2()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp1413 auto compose = [&SubRegAction](const CodeGenSubRegIndex *Sub1, in computeComposites()
1416 const RegMap &Img1 = SubRegAction.at(Sub1); in computeComposites()
/freebsd/contrib/googletest/docs/
H A Dadvanced.md680 10: void Sub1(int n) {
689 19: Sub1(1);
692 22: Sub1(9);
713 `Sub1()` the two failures come from respectively. (You could add an extra
714 message to each assertion in `Sub1()` to indicate the value of `n`, but that's
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp5786 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32, in tryInlineAsm() local
5790 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in tryInlineAsm()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp4003 SDValue Sub1 = N->getOperand(1); in foldRemainderIdiom() local
4015 if (Sub1.getOpcode() == ISD::MUL) { in foldRemainderIdiom()
4017 SDValue Mul0 = Sub1.getOperand(0); in foldRemainderIdiom()
4018 SDValue Mul1 = Sub1.getOperand(1); in foldRemainderIdiom()
4026 } else if (Sub1.getOpcode() == ISD::SHL) { in foldRemainderIdiom()
4028 SDValue Shl0 = Sub1.getOperand(0); in foldRemainderIdiom()
4029 SDValue Shl1 = Sub1.getOperand(1); in foldRemainderIdiom()
25473 SDValue Sub1 = getSubVectorSrc(Bop1, Index, SubVT); in narrowInsertExtractVectorBinOp() local
25478 if (!Sub0 || !Sub1) in narrowInsertExtractVectorBinOp()
25484 return DAG.getNode(BinOpcode, DL, SubVT, Sub0, Sub1, BinOp->getFlags()); in narrowInsertExtractVectorBinOp()
H A DTargetLowering.cpp11361 SDValue Sub1 = DAG.getNode(ISD::SUB, dl, VT, Quot, in expandFixedPointDiv() local
11365 Sub1, Quot); in expandFixedPointDiv()