| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelDAGToDAG.cpp | 254 SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl, MVT::i32, in tryInlineAsm() local
258 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in tryInlineAsm()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | ExpandLargeFpConvert.cpp | 376 Value *Sub1 = Builder.CreateSub(Builder.getIntN(BitWidthNew, BitWidth), in expandIToFP() local
381 Sub1, Builder.getIntN(BitWidthNew, FPMantissaWidth + 1)); in expandIToFP()
386 llvm::SwitchInst *SI = Builder.CreateSwitch(Sub1, SwDefault); in expandIToFP()
455 ExtractT62 = Builder.CreateTrunc(Sub1, Builder.getIntNTy(64)); in expandIToFP()
495 E0->addIncoming(Sub1, IfThen20); in expandIToFP()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelDAGToDAG.cpp | 220 SDValue Sub1 = in selectInlineAsm() local
224 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in selectInlineAsm()
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| /freebsd/contrib/llvm-project/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| H A D | BasicValueFactory.h | 224 const llvm::APSInt &Sub1(const llvm::APSInt &V) { in Sub1() function
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 855 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in SelectADD_SUB_I64() local
860 DL, MVT::i32, LHS, Sub1); in SelectADD_SUB_I64()
865 DL, MVT::i32, RHS, Sub1); in SelectADD_SUB_I64()
898 Sub1, in SelectADD_SUB_I64()
1060 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, SL, MVT::i32); in SelectMUL_LOHI() local
1062 MVT::i32, SDValue(Mad, 0), Sub1); in SelectMUL_LOHI()
1696 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in SelectFlatOffsetImpl() local
1701 DL, MVT::i32, N0, Sub1); in SelectFlatOffsetImpl()
1718 SDValue(Add, 0), Sub0, SDValue(Addc, 0), Sub1}; in SelectFlatOffsetImpl()
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| H A D | AMDGPULegalizerInfo.cpp | 4607 auto Sub1 = B.buildMergeLikeInstr(S64, {Sub1_Lo, Sub1_Hi}); in legalizeUnsignedDIV_REM64Impl() local
4664 Sel2, Sub1); in legalizeUnsignedDIV_REM64Impl()
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| H A D | AMDGPUISelLowering.cpp | 2132 SDValue Sub1 = DAG.getBitcast(VT, in LowerUDIVREM64() local
2183 SDValue Rem = DAG.getSelectCC(DL, C3, Zero, Sel2, Sub1, ISD::SETNE); in LowerUDIVREM64()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCodeEmitter.cpp | 435 const MCInst *Sub1 = MI.getOperand(1).getInst(); in encodeSingleInstruction() local
441 unsigned SubBits1 = getBinaryCodeForInstr(*Sub1, Fixups, STI); in encodeSingleInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 1950 unsigned Sub1 = MI.getOperand(2).getImm(); in evaluate() local
1955 if (Sub1 != SubLo && Sub1 != SubHi) in evaluate()
1959 assert(Sub1 != Sub2); in evaluate()
1960 bool LoIs1 = (Sub1 == SubLo); in evaluate()
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| H A D | HexagonBitSimplify.cpp | 466 unsigned Sub1 = I.getOperand(2).getImm(), Sub2 = I.getOperand(4).getImm(); in parseRegSequence() local
472 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence()
473 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence()
478 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.cpp | 1478 auto compose = [&SubRegAction](const CodeGenSubRegIndex *Sub1, in computeComposites()
1481 const RegMap &Img1 = SubRegAction.at(Sub1); in computeComposites()
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| /freebsd/contrib/googletest/docs/ |
| H A D | advanced.md | 674 10: void Sub1(int n) {
683 19: Sub1(1);
686 22: Sub1(9);
707 `Sub1()` the two failures come from respectively. (You could add an extra
708 message to each assertion in `Sub1()` to indicate the value of `n`, but that's
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 5802 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32, in tryInlineAsm() local
5806 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in tryInlineAsm()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 10859 SDValue Sub1 = DAG.getNode(ISD::SUB, dl, VT, Quot, in expandFixedPointDiv() local
10863 Sub1, Quot); in expandFixedPointDiv()
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| H A D | DAGCombiner.cpp | 24402 SDValue Sub1 = getSubVectorSrc(Bop1, Index, SubVT); in narrowInsertExtractVectorBinOp() local
24407 if (!Sub0 || !Sub1) in narrowInsertExtractVectorBinOp()
24413 return DAG.getNode(BinOpcode, SDLoc(Extract), SubVT, Sub0, Sub1, in narrowInsertExtractVectorBinOp()
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