| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonExpandCondsets.cpp | 181 Sub(Op.getSubReg()) {} in RegisterRef()
182 RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {} in RegisterRef()
185 return Reg == RR.Reg && Sub == RR.Sub; in operator ==()
189 return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub); in operator <()
193 unsigned Sub; member
200 unsigned getMaskForSub(unsigned Sub);
202 LaneBitmask getLaneMask(Register Reg, unsigned Sub);
263 unsigned HexagonExpandCondsets::getMaskForSub(unsigned Sub) { in INITIALIZE_PASS_DEPENDENCY()
264 switch (Sub) { in INITIALIZE_PASS_DEPENDENCY()
291 LaneBitmask HexagonExpandCondsets::getLaneMask(Register Reg, unsigned Sub) { in getLaneMask() argument
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| H A D | HexagonBitSimplify.cpp | 438 if (RR.Sub == 0) { in getSubregMask()
450 if (RR.Sub == Hexagon::isub_hi || RR.Sub == Hexagon::vsub_hi) in getSubregMask()
930 if (RR.Sub == 0) in getFinalVRegClass()
935 auto VerifySR = [&HRI] (const TargetRegisterClass *RC, unsigned Sub) -> void { in getFinalVRegClass() argument
937 assert(Sub == HRI.getHexagonSubRegIndex(*RC, Hexagon::ps_sub_lo) || in getFinalVRegClass()
938 Sub == HRI.getHexagonSubRegIndex(*RC, Hexagon::ps_sub_hi)); in getFinalVRegClass()
943 VerifySR(RC, RR.Sub); in getFinalVRegClass()
946 VerifySR(RC, RR.Sub); in getFinalVRegClass()
1377 .addReg(RS.Reg, 0, RS.Sub); in processBlock()
1378 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in processBlock()
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| H A D | BitTracker.cpp | 339 const auto &VC = composeWithSubRegIndex(*MRI.getRegClass(RR.Reg), RR.Sub); in getRegBitWidth()
344 (RR.Sub == 0) ? RR.Reg.asMCReg() : TRI.getSubReg(RR.Reg, RR.Sub); in getRegBitWidth()
366 if (!RR.Sub) in getCell()
368 BitMask M = mask(RR.Reg, RR.Sub); in getCell()
382 assert(RR.Sub == 0 && "Unexpected sub-register in definition"); in putCell()
707 BT::BitMask BT::MachineEvaluator::mask(Register Reg, unsigned Sub) const { in mask()
708 assert(Sub == 0 && "Generic BitTracker::mask called for Sub != 0"); in mask()
726 assert(RD.Sub == 0); in evaluate()
746 assert(RD.Sub == 0); in evaluate()
828 dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub) in visitPHI()
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| H A D | HexagonBlockRanges.h | 37 unsigned Sub; member
40 return Reg < R.Reg || (Reg == R.Reg && Sub < R.Sub);
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| /freebsd/contrib/llvm-project/llvm/lib/MC/MCDisassembler/ |
| H A D | MCExternalSymbolizer.cpp | 96 const MCExpr *Sub = nullptr; in tryAddingSymbolicOperand() local
101 Sub = MCSymbolRefExpr::create(Sym, Ctx); in tryAddingSymbolicOperand()
103 Sub = MCConstantExpr::create((int)SymbolicOp.SubtractSymbol.Value, Ctx); in tryAddingSymbolicOperand()
112 if (Sub) { in tryAddingSymbolicOperand()
115 LHS = MCBinaryExpr::createSub(Add, Sub, Ctx); in tryAddingSymbolicOperand()
117 LHS = MCUnaryExpr::createMinus(Sub, Ctx); in tryAddingSymbolicOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Support/ |
| H A D | CommandLine.cpp | 258 SubCommand &Sub = *SC; in removeOption() local
259 auto End = Sub.OptionsMap.end(); in removeOption()
261 auto I = Sub.OptionsMap.find(Name); in removeOption()
263 Sub.OptionsMap.erase(I); in removeOption()
267 for (auto *Opt = Sub.PositionalOpts.begin(); in removeOption()
268 Opt != Sub.PositionalOpts.end(); ++Opt) { in removeOption()
270 Sub.PositionalOpts.erase(Opt); in removeOption()
275 for (auto *Opt = Sub.SinkOpts.begin(); Opt != Sub.SinkOpts.end(); ++Opt) { in removeOption()
277 Sub.SinkOpts.erase(Opt); in removeOption()
281 else if (O == Sub.ConsumeAfterOpt) in removeOption()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64ExternalSymbolizer.cpp | 184 const MCExpr *Sub = nullptr; in tryAddingSymbolicOperand() local
189 Sub = MCSymbolRefExpr::create(Sym, Ctx); in tryAddingSymbolicOperand()
191 Sub = MCConstantExpr::create(SymbolicOp.SubtractSymbol.Value, Ctx); in tryAddingSymbolicOperand()
200 if (Sub) { in tryAddingSymbolicOperand()
203 LHS = MCBinaryExpr::createSub(Add, Sub, Ctx); in tryAddingSymbolicOperand()
205 LHS = MCUnaryExpr::createMinus(Sub, Ctx); in tryAddingSymbolicOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | DivRemPairs.cpp | 335 Instruction *Sub = BinaryOperator::CreateSub(X, Mul); in optimizeDivRem() local
371 Sub->insertAfter(Mul); in optimizeDivRem()
372 Sub->setDebugLoc(RemInst->getDebugLoc()); in optimizeDivRem()
392 Sub->setOperand(0, FrX); in optimizeDivRem()
406 Sub->setName(RemInst->getName() + ".decomposed"); in optimizeDivRem()
409 RemInst = Sub; in optimizeDivRem()
411 OrigRemInst->replaceAllUsesWith(Sub); in optimizeDivRem()
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| H A D | Reassociate.cpp | 863 if (TheNeg->getOpcode() == Instruction::Sub) { in NegateValue()
941 for (auto Op : {Instruction::Add, Instruction::Sub, Instruction::Mul, in shouldConvertOrWithNoCommonBitsToAdd()
977 static bool ShouldBreakUpSubtract(Instruction *Sub) { in ShouldBreakUpSubtract() argument
979 if (match(Sub, m_Neg(m_Value())) || match(Sub, m_FNeg(m_Value()))) in ShouldBreakUpSubtract()
983 if (isa<UndefValue>(Sub->getOperand(1))) in ShouldBreakUpSubtract()
988 Value *V0 = Sub->getOperand(0); in ShouldBreakUpSubtract()
990 isReassociableOp(V0, Instruction::Sub, Instruction::FSub)) in ShouldBreakUpSubtract()
992 Value *V1 = Sub->getOperand(1); in ShouldBreakUpSubtract()
994 isReassociableOp(V1, Instruction::Sub, Instruction::FSub)) in ShouldBreakUpSubtract()
996 Value *VB = Sub->user_back(); in ShouldBreakUpSubtract()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CalcSpillWeights.cpp | 51 unsigned Sub, HSub; in copyHint() local
54 Sub = MI->getOperand(0).getSubReg(); in copyHint()
58 Sub = MI->getOperand(1).getSubReg(); in copyHint()
67 return Sub == HSub ? HReg : Register(); in copyHint()
75 if (Sub) in copyHint()
76 return TRI.getMatchingSuperReg(CopiedPReg, Sub, RC); in copyHint()
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| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 122 for (MCPhysReg Sub : subregs(Reg)) { in getSubReg() local
124 return Sub; in getSubReg()
136 for (MCPhysReg Sub : subregs(Reg)) { in getSubRegIndex() local
137 if (Sub == SubReg) in getSubRegIndex()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | MVETailPredication.cpp | 331 const SCEV *Sub = SE->getMinusSCEV(SE->getBackedgeTakenCount(L), Div); in IsSafeActiveMask() local
332 LLVM_DEBUG(dbgs() << "ARM TP: - Sub = "; Sub->dump()); in IsSafeActiveMask()
337 Sub = SE->applyLoopGuards(Sub, L); in IsSafeActiveMask()
338 LLVM_DEBUG(dbgs() << "ARM TP: - (Guarded) = "; Sub->dump()); in IsSafeActiveMask()
340 if (!Sub->isZero()) { in IsSafeActiveMask()
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| /freebsd/contrib/llvm-project/compiler-rt/lib/ctx_profile/ |
| H A D | CtxInstrProfiling.cpp | 84 for (auto *Sub = Ctx->subContexts()[I]; Sub; Sub = Sub->next()) in validate() local
85 if (!ContextStartAddrs.find(reinterpret_cast<uint64_t>(Sub))) in validate()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCSectionGOFF.h | 32 MCSectionGOFF(StringRef Name, SectionKind K, MCSection *P, uint32_t Sub) in MCSectionGOFF() argument
34 Parent(P), Subsection(Sub) {} in MCSectionGOFF()
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | brcm-sata-phy.txt | 20 Sub-nodes:
23 Sub-nodes required properties:
27 Sub-nodes optional properties:
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| H A D | berlin-sata-phy.txt | 14 Sub-nodes:
17 Sub-nodes required properties:
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| H A D | phy-cadence-sierra.txt | 28 Sub-nodes:
33 Sub-node required properties:
41 Sub-node optional properties:
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| H A D | rockchip-usb-phy.txt | 15 Sub-nodes:
18 Sub-nodes
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| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | omap-abe-twl6040.txt | 28 * Sub Handset Mic
85 "SUBMIC", "Sub Handset Mic",
86 "Sub Handset Mic", "Main Mic Bias",
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| H A D | omap-twl4030.txt | 25 * Sub Mic
53 * Mic Bias 2 /* Used for Sub Mic or Digimic1 */
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86DynAllocaExpander.cpp | 44 enum Lowering { TouchAndSub, Sub, Probe }; enumerator
105 return Sub; in getLowering()
161 case Sub: in computeLowerings()
234 case Sub: in lower()
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| H A D | X86PartialReduction.cpp | 242 auto *Sub = dyn_cast<BinaryOperator>(LHS); in trySADReplacement() local
243 if (!Sub || Sub->getOpcode() != Instruction::Sub) in trySADReplacement()
258 Value *Op0 = getZeroExtendedVal(Sub->getOperand(0)); in trySADReplacement()
259 Value *Op1 = getZeroExtendedVal(Sub->getOperand(1)); in trySADReplacement()
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | marvell-pxa168.txt | 18 Sub-nodes:
21 Sub-nodes required properties:
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 305 MachineInstr *Sub = nullptr; in optimizeCompareInstr() local
333 Sub = &*I; in optimizeCompareInstr()
343 if (!MI && !Sub) in optimizeCompareInstr()
348 MI = Sub; in optimizeCompareInstr()
376 if (Sub) { in optimizeCompareInstr()
384 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
385 Sub->getOperand(2).getReg() == SrcReg) { in optimizeCompareInstr()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelperVectorOps.cpp | 447 GSub *Sub = cast<GSub>(MRI.getVRegDef(MO.getReg())); in matchSubOfVScale() local
448 GVScale *RHSVScale = cast<GVScale>(MRI.getVRegDef(Sub->getRHSReg())); in matchSubOfVScale()
459 B.buildAdd(Dst, Sub->getLHSReg(), VScale, Sub->getFlags()); in matchSubOfVScale()
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