| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelDAGToDAG.cpp | 1311 const EVT StoreVT = ST->getMemoryVT(); in tryStore() local
1312 if (!StoreVT.isSimple()) in tryStore()
1323 const unsigned ToTypeWidth = StoreVT.getSimpleVT().getSizeInBits(); in tryStore()
1362 const EVT StoreVT = ST->getMemoryVT(); in tryStoreVector() local
1363 assert(StoreVT.isSimple() && "Store value is not simple"); in tryStoreVector()
1378 const unsigned TotalWidth = StoreVT.getSimpleVT().getSizeInBits(); in tryStoreVector()
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| H A D | NVPTXISelLowering.cpp | 3519 const EVT StoreVT = in LowerReturn() local
3521 return correctParamType(RetVal, StoreVT, Outs[I].Flags, DAG, dl); in LowerReturn()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 5826 LLT StoreVT = MRI.getType(Reg); in handleD16VData() local
5827 assert(StoreVT.isVector() && StoreVT.getElementType() == S16); in handleD16VData()
5836 int NumElts = StoreVT.getNumElements(); in handleD16VData()
5843 if (StoreVT.getNumElements() == 2) { in handleD16VData()
5852 if (StoreVT.getNumElements() == 3) { in handleD16VData()
5862 if (StoreVT.getNumElements() == 4) { in handleD16VData()
5876 if (StoreVT == LLT::fixed_vector(3, S16)) { in handleD16VData()
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| H A D | AMDGPURegisterBankInfo.cpp | 1791 LLT StoreVT = MRI.getType(Reg); in handleD16VData() local
1792 if (!StoreVT.isVector() || StoreVT.getElementType() != S16) in handleD16VData()
1803 int NumElts = StoreVT.getNumElements(); in handleD16VData()
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| H A D | SIISelLowering.cpp | 8518 MVT StoreVT = VData.getSimpleValueType(); in lowerImage() local
8519 if (StoreVT.getScalarType() == MVT::f16) { in lowerImage()
10049 EVT StoreVT = VData.getValueType(); in handleD16VData() local
10052 if (!StoreVT.isVector()) in handleD16VData()
10056 unsigned NumElements = StoreVT.getVectorNumElements(); in handleD16VData()
10060 EVT IntStoreVT = StoreVT.changeTypeToInteger(); in handleD16VData()
10074 EVT IntStoreVT = StoreVT.changeTypeToInteger(); in handleD16VData()
10109 EVT::getIntegerVT(*DAG.getContext(), StoreVT.getStoreSizeInBits()); in handleD16VData()
10113 *DAG.getContext(), StoreVT.getVectorElementType(), NumElements + 1); in handleD16VData()
10120 assert(isTypeLegal(StoreVT)); in handleD16VData()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 691 virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT, in isStoreBitCastBeneficial() argument
695 return isLoadBitCastBeneficial(StoreVT, BitcastVT, DAG, MMO); in isStoreBitCastBeneficial()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 12238 EVT StoreVT = Value.getValueType(); in LowerVectorStore() local
12240 if (StoreVT == MVT::v1024i1 || StoreVT == MVT::v2048i1) in LowerVectorStore()
12243 if (StoreVT != MVT::v256i1 && StoreVT != MVT::v512i1) in LowerVectorStore()
12249 assert((StoreVT != MVT::v512i1 || Subtarget.hasMMA()) && in LowerVectorStore()
12251 assert((StoreVT != MVT::v256i1 || Subtarget.pairedVectorMemops()) && in LowerVectorStore()
12256 if (StoreVT == MVT::v512i1) { in LowerVectorStore()
16827 MVT StoreVT = Op1VT.getSimpleVT(); in PerformDAGCombine() local
16829 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 || in PerformDAGCombine()
16830 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32)) in PerformDAGCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 25487 static SDValue scalarizeVectorStore(StoreSDNode *Store, MVT StoreVT, in scalarizeVectorStore() argument
25490 assert(StoreVT.is128BitVector() && in scalarizeVectorStore()
25492 StoredVal = DAG.getBitcast(StoreVT, StoredVal); in scalarizeVectorStore()
25500 MVT StoreSVT = StoreVT.getScalarType(); in scalarizeVectorStore()
25501 unsigned NumElems = StoreVT.getVectorNumElements(); in scalarizeVectorStore()
25559 MVT StoreVT = StoredVal.getSimpleValueType(); in LowerStore() local
25560 if (StoreVT.is256BitVector() || StoreVT.is512BitVector()) { in LowerStore()
25566 if (StoreVT.is32BitVector()) in LowerStore()
25570 assert(StoreVT.is64BitVector() && "Unexpected VT"); in LowerStore()
25571 assert(TLI.getTypeAction(*DAG.getContext(), StoreVT) == in LowerStore()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 18757 EVT StoreVT = VT.getHalfNumVectorElementsVT(*DAG.getContext()); in PerformMVETruncCombine() local
18759 StoreVT = StoreVT.getHalfNumVectorElementsVT(*DAG.getContext()); in PerformMVETruncCombine()
18769 Ptr, MPI, StoreVT, Align(4)); in PerformMVETruncCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 23904 EVT StoreVT = in combineBoolVectorAndTruncateStore() local
23906 SDValue ExtendedBits = DAG.getZExtOrTrunc(VectorBits, DL, StoreVT); in combineBoolVectorAndTruncateStore()
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