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Searched refs:Stages (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/MCA/
H A DPipeline.cpp27 for (auto &S : Stages) in addEventListener()
32 return any_of(Stages, [](const std::unique_ptr<Stage> &S) { in hasWorkToProcess()
38 assert(!Stages.empty() && "Unexpected empty pipeline found!"); in run()
55 for (auto I = Stages.rbegin(), E = Stages.rend(); I != E && !Err; ++I) { in runCycle()
67 Stage &FirstStage = *Stages[0]; in runCycle()
77 for (const std::unique_ptr<Stage> &S : Stages) { in runCycle()
88 if (!Stages.empty()) { in appendStage()
89 Stage *Last = Stages.back().get(); in appendStage()
93 Stages.push_back(std::move(S)); in appendStage()
/freebsd/contrib/llvm-project/llvm/lib/Target/DirectX/
H A DDXIL.td296 class Stages<Version ver, list<DXILShaderStage> st> {
394 list<Stages> stages;
410 let stages = [Stages<DXIL1_0, [all_stages]>];
421 let stages = [Stages<DXIL1_0, [all_stages]>];
430 let stages = [Stages<DXIL1_0, [all_stages]>];
440 let stages = [Stages<DXIL1_0, [all_stages]>];
449 let stages = [Stages<DXIL1_0, [all_stages]>];
458 let stages = [Stages<DXIL1_0, [all_stages]>];
468 let stages = [Stages<DXIL1_0, [all_stages]>];
478 let stages = [Stages<DXIL1_0, [all_stages]>];
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H A DDXILOpBuilder.cpp155 llvm::SmallVector<OpStage> Stages; member
534 getPropIndex(ArrayRef(Prop->Stages), DXILVersion); in tryCreateOp()
539 uint16_t ValidShaderKindMask = Prop->Stages[*StIndexOrErr].ValidStages; in tryCreateOp()
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrItineraries.h114 const InstrStage *Stages = nullptr; ///< Array of stages selected
123 : SchedModel(SM), Stages(S), OperandCycles(OS), Forwardings(F), in InstrItineraryData()
138 return Stages + StageIdx; in beginStage()
144 return Stages + StageIdx; in endStage()
113 const InstrStage *Stages = nullptr; ///< Array of stages selected global() variable
H A DMCSubtargetInfo.h91 const InstrStage *Stages; // Instruction itinerary stages variable
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DModuloSchedule.h239 std::pair<unsigned, bool> Stages = RegToStageDiff[Reg]; in getStagesForReg() local
240 if ((int)CurStage > Schedule.getNumStages() - 1 && Stages.first == 0 && in getStagesForReg()
241 Stages.second) in getStagesForReg()
243 return Stages.first; in getStagesForReg()
253 std::pair<unsigned, bool> Stages = RegToStageDiff[Reg]; in getStagesForPhi() local
254 if (Stages.second) in getStagesForPhi()
255 return Stages.first; in getStagesForPhi()
256 return Stages.first - 1; in getStagesForPhi()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86PartialReduction.cpp313 unsigned Stages = Log2_32(NumSplits); in trySADReplacement() local
314 for (unsigned s = Stages; s > 0; --s) { in trySADReplacement()
371 unsigned Stages = Log2_32(NumElems); in matchAddReduction() local
372 for (unsigned i = 0; i != Stages; ++i) { in matchAddReduction()
H A DX86ISelLowering.cpp46366 unsigned Stages = Log2_32(VT.getVectorNumElements()); in combineVPDPBUSDPattern() local
46369 if (Stages > StageBias) { in combineVPDPBUSDPattern()
46372 for (unsigned i = Stages - StageBias; i > 0; --i) { in combineVPDPBUSDPattern()
46451 unsigned Stages = Log2_32(VT.getVectorNumElements()); in combineBasicSADPattern() local
46453 if (Stages > 3) { in combineBasicSADPattern()
46456 for(unsigned i = Stages - 3; i > 0; --i) { in combineBasicSADPattern()
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCSubtargetInfo.cpp257 WriteLatencyTable(WL), ReadAdvanceTable(RA), Stages(IS), in MCSubtargetInfo()
356 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths); in getInstrItineraryForCPU()
360 InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles, in initInstrItins()
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/
H A DPipeline.h63 SmallVector<std::unique_ptr<Stage>, 8> Stages; variable
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DWindowScheduler.cpp629 DenseMap<MachineInstr *, int> Cycles, Stages; in expand() local
635 Stages[MI] = std::get<2>(Info); in expand()
636 LLVM_DEBUG(dbgs() << "\tCycle " << Cycles[MI] << " [S." << Stages[MI] in expand()
640 std::move(Stages)); in expand()
H A DMachinePipeliner.cpp851 DenseMap<MachineInstr *, int> Cycles, Stages; in schedule() local
858 Stages[SU->getInstr()] = Schedule.stageScheduled(SU); in schedule()
864 Stages[KV.first] = Stages[KV.second]; in schedule()
869 std::move(Stages)); in schedule()
1340 DenseMap<MachineInstr *, unsigned> &Stages) { in computeScheduledInsts() argument
1362 Stages[MI] = Schedule.stageScheduled(SU); in computeScheduledInsts()
1600 Instr2StageTy &Stages) const { in computeLastUses()
1620 const auto InstrScore = [&Stages](MachineInstr *MI) { in computeLastUses()
1621 return Stages[MI] + MI->isPHI(); in computeLastUses()
1660 Instr2StageTy &Stages, in computeMaxSetPressure() argument
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DDXILEmitter.cpp297 auto Stages = Rec->getValueAsListOfDefs("shader_stages"); in getStageMaskString() local
298 if (Stages.empty()) { in getStageMaskString()
301 for (const auto *S : Stages) { in getStageMaskString()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetItinerary.td114 list<InstrStage> Stages = stages;
/freebsd/lib/clang/libllvm/
H A DMakefile1070 SRCS_EXT+= MCA/Stages/DispatchStage.cpp
1071 SRCS_EXT+= MCA/Stages/EntryStage.cpp
1072 SRCS_EXT+= MCA/Stages/ExecuteStage.cpp
1073 SRCS_EXT+= MCA/Stages/InOrderIssueStage.cpp
1074 SRCS_EXT+= MCA/Stages/InstructionTables.cpp
1075 SRCS_EXT+= MCA/Stages/MicroOpQueueStage.cpp
1076 SRCS_EXT+= MCA/Stages/RetireStage.cpp
1077 SRCS_EXT+= MCA/Stages/Stage.cpp
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp12887 unsigned Stages = Log2_32(Op.getValueType().getVectorNumElements()); in matchBinOpReduction() local
12889 for (unsigned i = 0; i < Stages; ++i) { in matchBinOpReduction()
/freebsd/contrib/llvm-project/llvm/include/llvm/Testing/Demangle/
H A DDemangleTestCases.inc28934 {"_ZL6Stages", "Stages"},