Searched refs:StVal (Results 1 – 4 of 4) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 6863 SDValue StVal = ST->getValue(); in WidenVecOp_STORE()
6864 EVT StVT = StVal.getValueType(); in WidenVecOp_STORE()
6873 StVal = GetWidenedVector(StVal); in WidenVecOp_STORE()
6877 return DAG.getStoreVP(ST->getChain(), DL, StVal, ST->getBasePtr(), in WidenVecOp_STORE()
6906 SDValue StVal = ST->getValue(); in WidenVecOp_VP_STORE()
6911 StVal = GetWidenedVector(StVal); in WidenVecOp_VP_STORE()
6924 assert(getTypeAction(StVal.getValueType()) == in WidenVecOp_VP_STORE()
6927 StVal in WidenVecOp_VP_STORE()
6859 SDValue StVal = ST->getValue(); WidenVecOp_STORE() local
6902 SDValue StVal = ST->getValue(); WidenVecOp_VP_STORE() local
6942 SDValue StVal = SST->getValue(); WidenVecOp_VP_STRIDED_STORE() local
6974 SDValue StVal = MST->getValue(); WidenVecOp_MSTORE() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 1562 SDValue StVal, SDValue &InGlue, in LowerUnalignedStoreParam() argument
1566 StVal = DAG.getNode(ISD::BITCAST, dl, ElementType, StVal); in LowerUnalignedStoreParam()
1572 SDValue ShiftVal = DAG.getNode(ISD::SRL, dl, ElementType, StVal, in LowerUnalignedStoreParam()
1787 SDValue StVal = OutVals[OIdx]; in LowerCall() local
1793 if (PromoteScalarIntegerPTX(StVal.getValueType(), &PromotedVT)) { in LowerCall()
1796 StVal = DAG.getNode(Ext, dl, PromotedVT, StVal); in LowerCall()
1801 SDValue srcAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StVal, in LowerCall()
1803 StVal = DAG.getLoad(EltVT, dl, TempChain, srcAddr, MachinePointerInfo(), in LowerCall()
1808 StVal = DAG.getNode(Outs[OIdx].Flags.isSExt() ? ISD::SIGN_EXTEND in LowerCall()
1810 dl, MVT::i32, StVal); in LowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 16061 SDValue &StVal = Ops[Ops.size() - 2]; in TryCombineBaseUpdate() local
16062 StVal = DAG.getNode(ISD::BITCAST, dl, AlignedVecTy, StVal); in TryCombineBaseUpdate()
16554 SDValue StVal = St->getValue(); in PerformTruncatingStoreCombine() local
16555 EVT VT = StVal.getValueType(); in PerformTruncatingStoreCombine()
16583 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal); in PerformTruncatingStoreCombine()
16812 SDValue StVal = St->getValue(); in PerformSTORECombine() local
16813 EVT VT = StVal.getValueType(); in PerformSTORECombine()
16836 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR && in PerformSTORECombine()
16837 StVal.getNode()->hasOneUse()) { in PerformSTORECombine()
16843 St->getChain(), DL, StVal.getNode()->getOperand(isBigEndian ? 1 : 0), in PerformSTORECombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 21816 SDValue StVal = St.getValue(); in replaceZeroVectorStore() local
21817 EVT VT = StVal.getValueType(); in replaceZeroVectorStore()
21832 if (StVal.getOpcode() != ISD::BUILD_VECTOR) in replaceZeroVectorStore()
21838 if (!StVal.hasOneUse()) in replaceZeroVectorStore()
21855 SDValue EltVal = StVal.getOperand(I); in replaceZeroVectorStore()
21883 SDValue StVal = St.getValue(); in replaceSplatVectorStore() local
21884 EVT VT = StVal.getValueType(); in replaceSplatVectorStore()
21908 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT) in replaceSplatVectorStore()
21913 SplatVal = StVal.getOperand(1); in replaceSplatVectorStore()
21914 else if (StVal.getOperand(1) != SplatVal) in replaceSplatVectorStore()
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