Searched refs:StVal (Results 1 – 4 of 4) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 7325 SDValue StVal = ST->getValue(); in WidenVecOp_STORE() local
7326 EVT StVT = StVal.getValueType(); in WidenVecOp_STORE()
7335 StVal = GetWidenedVector(StVal); in WidenVecOp_STORE()
7339 return DAG.getStoreVP(ST->getChain(), DL, StVal, ST->getBasePtr(), in WidenVecOp_STORE()
7367 SDValue StVal = ST->getValue(); in WidenVecOp_VP_STORE() local
7372 StVal = GetWidenedVector(StVal); in WidenVecOp_VP_STORE()
7385 assert(getTypeAction(StVal.getValueType()) == in WidenVecOp_VP_STORE()
7388 StVal = GetWidenedVector(StVal); in WidenVecOp_VP_STORE()
7392 StVal.getValueType().getVectorElementCount() && in WidenVecOp_VP_STORE()
7394 return DAG.getStoreVP(ST->getChain(), dl, StVal, ST->getBasePtr(), in WidenVecOp_VP_STORE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 1338 SDValue StVal, SDValue &InGlue, in LowerUnalignedStoreParam() argument
1342 StVal = DAG.getNode(ISD::BITCAST, dl, ElementType, StVal); in LowerUnalignedStoreParam()
1348 SDValue ShiftVal = DAG.getNode(ISD::SRL, dl, ElementType, StVal, in LowerUnalignedStoreParam()
1622 SDValue StVal; in LowerCall() local
1629 StVal = DAG.getLoad(EltVT, dl, TempChain, SrcAddr, MPI, PartAlign); in LowerCall()
1631 StVal = ArgOutVals[I]; in LowerCall()
1633 auto PromotedVT = promoteScalarIntegerPTX(StVal.getValueType()); in LowerCall()
1634 if (PromotedVT != StVal.getValueType()) { in LowerCall()
1635 StVal = DAG.getNode(getExtOpcode(ArgOuts[I].Flags), dl, PromotedVT, in LowerCall()
1636 StVal); in LowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 16159 SDValue &StVal = Ops[Ops.size() - 2]; in TryCombineBaseUpdate() local
16160 StVal = DAG.getNode(ISD::BITCAST, dl, AlignedVecTy, StVal); in TryCombineBaseUpdate()
16628 SDValue StVal = St->getValue(); in PerformTruncatingStoreCombine() local
16629 EVT VT = StVal.getValueType(); in PerformTruncatingStoreCombine()
16657 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal); in PerformTruncatingStoreCombine()
16886 SDValue StVal = St->getValue(); in PerformSTORECombine() local
16887 EVT VT = StVal.getValueType(); in PerformSTORECombine()
16910 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR && in PerformSTORECombine()
16911 StVal.getNode()->hasOneUse()) { in PerformSTORECombine()
16917 St->getChain(), DL, StVal.getNode()->getOperand(isBigEndian ? 1 : 0), in PerformSTORECombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 22828 SDValue StVal = St.getValue(); in replaceZeroVectorStore() local
22829 EVT VT = StVal.getValueType(); in replaceZeroVectorStore()
22844 if (StVal.getOpcode() != ISD::BUILD_VECTOR) in replaceZeroVectorStore()
22850 if (!StVal.hasOneUse()) in replaceZeroVectorStore()
22867 SDValue EltVal = StVal.getOperand(I); in replaceZeroVectorStore()
22895 SDValue StVal = St.getValue(); in replaceSplatVectorStore() local
22896 EVT VT = StVal.getValueType(); in replaceSplatVectorStore()
22920 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT) in replaceSplatVectorStore()
22925 SplatVal = StVal.getOperand(1); in replaceSplatVectorStore()
22926 else if (StVal.getOperand(1) != SplatVal) in replaceSplatVectorStore()
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