| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatterns.td | 373 def Sub: pf2<sub>; def Or: pf2<or>; def Srl: pf2<srl>;
1186 def: OpR_RI_pat<S2_lsr_i_r, Srl, i32, I32, u5_0ImmPred>;
1189 def: OpR_RI_pat<S2_lsr_i_p, Srl, i64, I64, u6_0ImmPred>;
1192 def: OpR_RI_pat<S2_lsr_i_vh, Srl, v4i16, V4I16, u4_0ImmPred>;
1195 def: OpR_RI_pat<S2_lsr_i_vh, Srl, v2i32, V2I32, u5_0ImmPred>;
1199 def: OpR_RR_pat<S2_lsr_r_r, Srl, i32, I32, I32>;
1202 def: OpR_RR_pat<S2_lsr_r_p, Srl, i64, I64, I32>;
1311 def: AccRRI_pat<S2_lsr_i_r_acc, Add, Su<Srl>, I32, u5_0ImmPred>;
1312 def: AccRRI_pat<S2_lsr_i_r_nac, Sub, Su<Srl>, I32, u5_0ImmPred>;
1313 def: AccRRI_pat<S2_lsr_i_r_and, And, Su<Srl>, I32, u5_0ImmPred>;
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 68 SDValue Srl = In.getOperand(0); in isExtractHiElt() local
69 if (Srl.getOpcode() == ISD::SRL) { in isExtractHiElt()
70 if (ConstantSDNode *ShiftAmt = dyn_cast<ConstantSDNode>(Srl.getOperand(1))) { in isExtractHiElt()
72 Out = stripBitcast(Srl.getOperand(0)); in isExtractHiElt()
2310 const SDValue &Srl = N->getOperand(0); in SelectS_BFE() local
2311 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(Srl.getOperand(1)); in SelectS_BFE()
2320 ReplaceNode(N, getBFE32(false, SDLoc(N), Srl.getOperand(0), ShiftVal, in SelectS_BFE()
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| H A D | SIISelLowering.cpp | 13471 SDValue Srl = DAG.getNode(ISD::SRL, SL, MVT::i32, Elt, in performExtractVectorEltCombine() local
13473 DCI.AddToWorklist(Srl.getNode()); in performExtractVectorEltCombine()
13476 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, VecEltAsIntVT, Srl); in performExtractVectorEltCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64Combine.td | 285 // Combines Mul(And(Srl(X, 15), 0x10001), 0xffff) into CMLTz
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| H A D | AArch64ISelLowering.cpp | 18179 SDValue Srl = And.getOperand(0); in performMulVectorCmpZeroCombine() local
18184 !ISD::isConstantSplatVector(Srl.getOperand(1).getNode(), V3)) in performMulVectorCmpZeroCombine()
18197 SDValue In = DAG.getNode(AArch64ISD::NVCAST, DL, HalfVT, Srl.getOperand(0)); in performMulVectorCmpZeroCombine()
22119 static SDValue trySimplifySrlAddToRshrnb(SDValue Srl, SelectionDAG &DAG, in trySimplifySrlAddToRshrnb() argument
22121 EVT VT = Srl->getValueType(0); in trySimplifySrlAddToRshrnb()
22135 SDLoc DL(Srl); in trySimplifySrlAddToRshrnb()
22138 if (!canLowerSRLToRoundingShiftForVT(Srl, ResVT, DAG, ShiftValue, RShOperand)) in trySimplifySrlAddToRshrnb()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 470 SDValue Srl = N1.getOperand(0); in PreprocessISelDAG() local
472 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) || in PreprocessISelDAG()
491 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32, in PreprocessISelDAG()
492 Srl.getOperand(0), in PreprocessISelDAG()
493 CurDAG->getConstant(Srl_imm + TZ, SDLoc(Srl), in PreprocessISelDAG()
496 Srl, in PreprocessISelDAG()
497 CurDAG->getConstant(And_imm, SDLoc(Srl), MVT::i32)); in PreprocessISelDAG()
499 N1, CurDAG->getConstant(TZ, SDLoc(Srl), MVT::i32)); in PreprocessISelDAG()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 2060 SDValue Srl = DAG.getNode(ISD::SRL, DL, XVT, X, Eight); in foldMaskAndShiftToExtract() local
2061 SDValue And = DAG.getNode(ISD::AND, DL, XVT, Srl, NewMask); in foldMaskAndShiftToExtract()
2073 insertDAGNode(DAG, N, Srl); in foldMaskAndShiftToExtract()
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| H A D | X86ISelLowering.cpp | 30247 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, R, in LowerRotate() local
30249 return DAG.getNode(ISD::OR, DL, VT, Shl, Srl); in LowerRotate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 13681 SDValue Srl = DAG.getNode(ISD::SRL, DL, MVT::i64, Op0, Op1); in performTRUNCATECombine()
13682 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Srl); in performTRUNCATECombine()
13709 SDValue Srl = DAG.getNode(ISD::SRL, DL, MVT::i64, Op0, Op1); in performANDCombine()
13710 SDValue And = DAG.getNode(ISD::AND, DL, MVT::i64, Srl, in performANDCombine()
14031 SDValue Srl = And.getOperand(0); in combineVectorMulToSraBitcast()
14036 !ISD::isConstantSplatVector(Srl.getOperand(1).getNode(), V3)) in combineVectorMulToSraBitcast()
14048 SDValue Cast = DAG.getNode(ISD::BITCAST, DL, HalfVT, Srl.getOperand(0)); in combineVectorMulToSraBitcast()
13678 SDValue Srl = DAG.getNode(ISD::SRL, DL, MVT::i64, Op0, Op1); performTRUNCATECombine() local
13706 SDValue Srl = DAG.getNode(ISD::SRL, DL, MVT::i64, Op0, Op1); performANDCombine() local
14028 SDValue Srl = And.getOperand(0); combineVectorMulToSraBitcast() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 7086 auto Srl = MIRBuilder.buildLShr(DstTy, R, ExponentSub); in lowerFPTOSI() local
7092 R = MIRBuilder.buildSelect(DstTy, CmpGt, Shl, Srl); in lowerFPTOSI()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 4814 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact); in visitSDIVLike() local
4815 AddToWorklist(Srl.getNode()); in visitSDIVLike()
4816 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Srl); in visitSDIVLike()
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| /freebsd/share/misc/ |
| H A D | usb_vendors | 18254 152b MIR Srl
22261 25dd Bit4id Srl
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| H A D | pci_vendors | 25026 1ab9 Espia Srl
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