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Searched refs:SrcVec (Results 1 – 19 of 19) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp187 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector() local
198 .addReg(SrcVec) in RebuildVector()
209 SrcVec = DstReg; in RebuildVector()
212 BuildMI(MBB, Pos, DL, TII->get(R600::COPY), Reg).addReg(SrcVec); in RebuildVector()
H A DSIISelLowering.cpp4749 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); in emitIndirectDst() local
4753 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg()); in emitIndirectDst()
4761 SrcVec->getReg(), in emitIndirectDst()
4772 .add(*SrcVec) in emitIndirectDst()
4791 .addReg(SrcVec->getReg()) in emitIndirectDst()
4801 .addReg(SrcVec->getReg()) in emitIndirectDst()
4818 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg, Offset, in emitIndirectDst()
8705 SDValue SrcVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, in LowerINTRINSIC_WO_CHAIN() local
8708 SDValue SrcHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, SrcVec, in LowerINTRINSIC_WO_CHAIN()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineVectorOps.cpp399 Value *SrcVec = EI.getVectorOperand(); in visitExtractElementInst() local
401 if (Value *V = simplifyExtractElementInst(SrcVec, Index, in visitExtractElementInst()
432 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(SrcVec)) { in visitExtractElementInst()
461 if (auto *Phi = dyn_cast<PHINode>(SrcVec)) in visitExtractElementInst()
469 if (match(SrcVec, m_UnOp(UO)) && cheapToScalarize(SrcVec, Index)) { in visitExtractElementInst()
479 if (match(SrcVec, m_BinOp(BO)) && cheapToScalarize(SrcVec, Index) && in visitExtractElementInst()
490 if (match(SrcVec, m_Cmp(Pred, m_Value(X), m_Value(Y))) && in visitExtractElementInst()
491 cheapToScalarize(SrcVec, Index)) { in visitExtractElementInst()
495 CmpInst *SrcCmpInst = cast<CmpInst>(SrcVec); in visitExtractElementInst()
500 if (auto *I = dyn_cast<Instruction>(SrcVec)) { in visitExtractElementInst()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp480 Register SrcVec = Left; in matchINS() local
484 SrcVec = Right; in matchINS()
488 MatchInfo = std::make_tuple(DstVec, DstLane, SrcVec, SrcLane); in matchINS()
498 Register DstVec, SrcVec; in applyINS() local
500 std::tie(DstVec, DstLane, SrcVec, SrcLane) = MatchInfo; in applyINS()
502 auto Extract = Builder.buildExtractVectorElement(ScalarTy, SrcVec, SrcCst); in applyINS()
/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp1513 GenericValue TempDst, TempSrc, SrcVec; in executeBitCastInst() local
1525 SrcVec = Src; in executeBitCastInst()
1531 SrcVec.AggregateVal.push_back(Src); in executeBitCastInst()
1552 APInt::floatToBits(SrcVec.AggregateVal[i].FloatVal); in executeBitCastInst()
1557 APInt::doubleToBits(SrcVec.AggregateVal[i].DoubleVal); in executeBitCastInst()
1560 TempSrc.AggregateVal[i].IntVal = SrcVec.AggregateVal[i].IntVal; in executeBitCastInst()
/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DVerifier.cpp3304 bool SrcVec = SrcTy->isVectorTy(); in visitUIToFPInst() local
3307 Check(SrcVec == DstVec, in visitUIToFPInst()
3314 if (SrcVec && DstVec) in visitUIToFPInst()
3327 bool SrcVec = SrcTy->isVectorTy(); in visitSIToFPInst() local
3330 Check(SrcVec == DstVec, in visitSIToFPInst()
3337 if (SrcVec && DstVec) in visitSIToFPInst()
3350 bool SrcVec = SrcTy->isVectorTy(); in visitFPToUIInst() local
3353 Check(SrcVec == DstVec, in visitFPToUIInst()
3359 if (SrcVec && DstVec) in visitFPToUIInst()
3372 bool SrcVec = SrcTy->isVectorTy(); in visitFPToSIInst() local
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIRBuilder.h1042 CallInst *CreateExtractVector(Type *DstType, Value *SrcVec, Value *Idx,
1045 {DstType, SrcVec->getType()}, {SrcVec, Idx}, nullptr,
1050 CallInst *CreateInsertVector(Type *DstType, Value *SrcVec, Value *SubVec,
1053 {DstType, SubVec->getType()}, {SrcVec, SubVec, Idx},
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVectorCombine.cpp643 Value *SrcVec; in foldInsExtFNeg() local
647 m_ExtractElt(m_Value(SrcVec), m_SpecificInt(Index)))))) in foldInsExtFNeg()
652 if (SrcVec->getType() != VecTy) in foldInsExtFNeg()
688 Value *VecFNeg = Builder.CreateFNegFMF(SrcVec, FNeg); in foldInsExtFNeg()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCodeGenFunction.cpp3053 llvm::Value *CodeGenFunction::emitBoolVecConversion(llvm::Value *SrcVec, in emitBoolVecConversion() argument
3056 auto *SrcTy = cast<llvm::FixedVectorType>(SrcVec->getType()); in emitBoolVecConversion()
3059 return SrcVec; in emitBoolVecConversion()
3066 return Builder.CreateShuffleVector(SrcVec, ShuffleMask, Name); in emitBoolVecConversion()
H A DCodeGenFunction.h5150 llvm::Value *emitBoolVecConversion(llvm::Value *SrcVec,
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp3231 auto [Dst, DstTy, SrcVec, SrcVecTy, Idx, IdxTy] = MI.getFirst3RegLLTs(); in bitcastExtractVectorElt()
3238 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); in bitcastExtractVectorElt()
3367 auto [Dst, DstTy, SrcVec, SrcVecTy, Val, ValTy, Idx, IdxTy] = in bitcastInsertVectorElt()
3379 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); in bitcastInsertVectorElt()
4541 auto [DstReg, SrcVec] = MI.getFirst2Regs(); in fewerElementsVectorExtractInsertVectorElt()
4555 LLT VecTy = MRI.getType(SrcVec); in fewerElementsVectorExtractInsertVectorElt()
4571 LLT GCDTy = extractGCDType(VecParts, VecTy, NarrowVecTy, SrcVec); in fewerElementsVectorExtractInsertVectorElt()
7529 Register SrcVec = MI.getOperand(1).getReg(); in lowerExtractInsertVectorElt() local
7536 LLT VecTy = MRI.getType(SrcVec); in lowerExtractInsertVectorElt()
7543 extractParts(SrcVec, EltTy, NumElts, SrcRegs, MIRBuilder, MRI); in lowerExtractInsertVectorElt()
[all …]
H A DCombinerHelper.cpp4125 Register SrcVec = MI.getOperand(1).getReg(); in matchExtractVecEltBuildVec() local
4126 LLT SrcTy = MRI.getType(SrcVec); in matchExtractVecEltBuildVec()
4136 MachineInstr *SrcVecMI = MRI.getVRegDef(SrcVec); in matchExtractVecEltBuildVec()
4146 if (!MRI.hasOneNonDBGUse(SrcVec) && in matchExtractVecEltBuildVec()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp6054 SDValue SrcVec = SrcExtract.getOperand(0); in getFauxShuffleMask() local
6055 EVT SrcVT = SrcVec.getValueType(); in getFauxShuffleMask()
6066 Ops.push_back(SrcVec); in getFauxShuffleMask()
6069 Ops.push_back(SrcVec); in getFauxShuffleMask()
8459 static SDValue createVariablePermute(MVT VT, SDValue SrcVec, SDValue IndicesVec, in createVariablePermute() argument
8486 if (SrcVec.getValueSizeInBits() != SizeInBits) { in createVariablePermute()
8487 if ((SrcVec.getValueSizeInBits() % SizeInBits) == 0) { in createVariablePermute()
8489 unsigned Scale = SrcVec.getValueSizeInBits() / SizeInBits; in createVariablePermute()
8495 createVariablePermute(VT, SrcVec, IndicesVec, DL, DAG, Subtarget); in createVariablePermute()
8499 } else if (SrcVec.getValueSizeInBits() < SizeInBits) { in createVariablePermute()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp1991 auto GetConvertedLane = [](SDValue Op, unsigned &Opcode, SDValue &SrcVec, in LowerConvertLow()
2014 SrcVec = ExtractVector.getOperand(0); in LowerConvertLow()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp861 auto IsBuildFromExtracts = [this,&Values] (SDValue &SrcVec, in buildHvxVectorReg()
883 SrcVec = Vec; in buildHvxVectorReg()
863 __anona938eeb30302(SDValue &SrcVec, SmallVectorImpl<int> &SrcIdx) buildHvxVectorReg() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp5065 SDValue SrcVec = (unsigned)SrcVecIdx >= VRegsPerSrc ? V2 : V1; in lowerShuffleViaVRegSplitting()
5066 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, M1VT, SrcVec, in lowerShuffleViaVRegSplitting()
12990 SDValue SrcVec = RHS.getOperand(0); in combineBinOpOfExtractToReduceTree()
12991 EVT SrcVecVT = SrcVec.getValueType(); in combineBinOpOfExtractToReduceTree()
13004 LHS.getOperand(0) == SrcVec && isa<ConstantSDNode>(LHS.getOperand(1))) { in combineBinOpOfExtractToReduceTree()
13009 SDValue Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ReduceVT, SrcVec, in combineBinOpOfExtractToReduceTree()
13031 SDValue Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ReduceVT, SrcVec, in combineBinOpOfExtractToReduceTree()
5064 SDValue SrcVec = (unsigned)SrcVecIdx >= VRegsPerSrc ? V2 : V1; lowerShuffleViaVRegSplitting() local
12987 SDValue SrcVec = RHS.getOperand(0); combineBinOpOfExtractToReduceTree() local
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp13269 SDValue SrcVec = V1; in LowerVECTOR_SHUFFLE() local
13272 SrcVec = V2; in LowerVECTOR_SHUFFLE()
13284 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV), in LowerVECTOR_SHUFFLE()
20223 SDValue SrcVec = Elt0->getOperand(0)->getOperand(0); in performBuildVectorCombine() local
20224 if (SrcVec.getValueType() == MVT::v4f16 || in performBuildVectorCombine()
20225 SrcVec.getValueType() == MVT::v4bf16) { in performBuildVectorCombine()
20227 DAG.getNode(ISD::FP_EXTEND, DL, MVT::v4f32, SrcVec); in performBuildVectorCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp15110 SDValue SrcVec = Ext1.getOperand(0); in DAGCombineBuildVector() local
15114 SrcVec, DAG.getIntPtrConstant(SubvecIdx, dl)); in DAGCombineBuildVector()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp26466 SDValue SrcVec = Scalar.getOperand(0); in visitSCALAR_TO_VECTOR() local
26467 EVT SrcVT = SrcVec.getValueType(); in visitSCALAR_TO_VECTOR()
26475 SrcVT, SDLoc(N), SrcVec, DAG.getUNDEF(SrcVT), Mask, DAG); in visitSCALAR_TO_VECTOR()