Searched refs:SrcRegBank (Results 1 – 4 of 4) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 930 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select() local
933 if (SrcRegBank.getID() == ARM::FPRRegBankID) { in select()
958 if (SrcRegBank.getID() != DstRegBank.getID()) { in select()
964 if (SrcRegBank.getID() != ARM::GPRRegBankID) { in select()
1025 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select() local
1028 if (SrcRegBank.getID() != DstRegBank.getID()) { in select()
1035 if (SrcRegBank.getID() != ARM::GPRRegBankID) { in select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 285 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy() local
290 if (DstSize > SrcSize && SrcRegBank.getID() == X86::GPRRegBankID && in selectCopy()
294 getRegClass(MRI.getType(SrcReg), SrcRegBank); in selectCopy()
326 if (SrcRegBank.getID() == X86::GPRRegBankID && in selectCopy()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 954 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in getRegClassesForCopy() local
967 if (SrcRegBank != DstRegBank && (DstSize == 1 && SrcSize == 1)) in getRegClassesForCopy()
970 return {getMinClassForRegBank(SrcRegBank, SrcSize, true), in getRegClassesForCopy()
1012 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy() local
1039 if (getMinSizeForRegBank(SrcRegBank) > DstSize) { in selectCopy()
1051 getMinClassForRegBank(SrcRegBank, DstSize, /* GetAllRegSet */ true); in selectCopy()
1058 getMinClassForRegBank(SrcRegBank, DstSize, /* GetAllRegSet */ true); in selectCopy()
1089 assert(SrcRegBank.getID() == AArch64::GPRRegBankID); in selectCopy()
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