Searched refs:SrcReg0Sub1 (Results 1 – 2 of 2) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 7806 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitUnaryOp() local
7810 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1); in splitScalar64BitUnaryOp()
8039 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitBinaryOp() local
8056 .add(SrcReg0Sub1) in splitScalar64BitBinaryOp()
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| H A D | SIISelLowering.cpp | 5089 MachineOperand SrcReg0Sub1 = TII->buildExtractSubRegOrImm( in EmitInstrWithCustomInserter() local
5105 .add(SrcReg0Sub1) in EmitInstrWithCustomInserter()
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