| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 724 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping() local
726 DstRB = SrcRB; in getInstrMapping()
727 else if (!SrcRB) in getInstrMapping()
728 SrcRB = DstRB; in getInstrMapping()
731 assert(DstRB && SrcRB && "Both RegBank were nullptr"); in getInstrMapping()
734 DefaultMappingID, copyCost(*DstRB, *SrcRB, Size), in getInstrMapping()
735 getCopyMapping(DstRB->getID(), SrcRB->getID(), Size), in getInstrMapping()
750 const RegisterBank &SrcRB = in getInstrMapping() local
753 DefaultMappingID, copyCost(DstRB, SrcRB, Size), in getInstrMapping()
754 getCopyMapping(DstRB.getID(), SrcRB.getID(), Size), in getInstrMapping()
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| H A D | AArch64InstructionSelector.cpp | 2864 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in select() local
2866 assert(SrcRB.getID() == DstRB.getID() && "Wrong extract regbank!"); in select()
2868 if (SrcRB.getID() == AArch64::GPRRegBankID) { in select()
3287 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in select() local
3289 if (DstRB.getID() != SrcRB.getID()) { in select()
3300 const TargetRegisterClass *SrcRC = getRegClassForTypeOnBank(SrcTy, SrcRB); in select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCRegisterBankInfo.cpp | 211 const RegisterBank &SrcRB = SrcIsGPR ? PPC::GPRRegBank : PPC::VECRegBank; in getInstrMapping() local
214 MappingID, Cost, getCopyMapping(DstRB.getID(), SrcRB.getID(), DstSize), in getInstrMapping()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 831 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectTruncOrPtrToInt() local
833 if (DstRB.getID() != SrcRB.getID()) { in selectTruncOrPtrToInt()
840 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); in selectTruncOrPtrToInt()
960 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectAnyext() local
962 assert(DstRB.getID() == SrcRB.getID() && in selectAnyext()
969 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); in selectAnyext()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 1569 auto SrcRB = MRI.getRegBankOrNull(MI->getOperand(1).getReg()); in isLaneMaskFromSameBlock() local
1570 if (DstRB && SrcRB && DstRB->getID() == AMDGPU::VCCRegBankID && in isLaneMaskFromSameBlock()
1571 SrcRB->getID() == AMDGPU::SGPRRegBankID) in isLaneMaskFromSameBlock()
2432 const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_TRUNC() local
2437 DstRB = SrcRB; in selectG_TRUNC()
2440 if (SrcRB != DstRB) in selectG_TRUNC()
2450 TRI.getRegClassForSizeOnBank(SrcSize, *SrcRB); in selectG_TRUNC()
3100 const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_PTRMASK() local
3103 if (DstRB != SrcRB) // Should only happen for hand written MIR. in selectG_PTRMASK()
3130 const TargetRegisterClass *SrcRC = TRI.getRegClassForTypeOnBank(Ty, *SrcRB); in selectG_PTRMASK()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineVerifier.cpp | 1203 const RegisterBank *SrcRB = RBI->getRegBank(Src, *MRI, *TRI); in verifyPreISelGenericInstruction() local
1207 if ((SrcRB && DstRB && SrcRB != DstRB) || (DstRB && !SrcRB)) { in verifyPreISelGenericInstruction()
|