| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 713 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping() local
715 DstRB = SrcRB; in getInstrMapping()
716 else if (!SrcRB) in getInstrMapping()
717 SrcRB = DstRB; in getInstrMapping()
720 assert(DstRB && SrcRB && "Both RegBank were nullptr"); in getInstrMapping()
723 DefaultMappingID, copyCost(*DstRB, *SrcRB, Size), in getInstrMapping()
724 getCopyMapping(DstRB->getID(), SrcRB->getID(), Size), in getInstrMapping()
739 const RegisterBank &SrcRB = in getInstrMapping() local
742 DefaultMappingID, copyCost(DstRB, SrcRB, Size), in getInstrMapping()
743 getCopyMapping(DstRB.getID(), SrcRB.getID(), Size), in getInstrMapping()
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| H A D | AArch64InstructionSelector.cpp | 2735 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in select() local
2737 assert(SrcRB.getID() == DstRB.getID() && "Wrong extract regbank!"); in select()
2739 if (SrcRB.getID() == AArch64::GPRRegBankID) { in select()
3152 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in select() local
3154 if (DstRB.getID() != SrcRB.getID()) { in select()
3165 const TargetRegisterClass *SrcRC = getRegClassForTypeOnBank(SrcTy, SrcRB); in select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCRegisterBankInfo.cpp | 230 const RegisterBank &SrcRB = SrcIsGPR ? PPC::GPRRegBank : PPC::VECRegBank; in getInstrMapping() local
233 MappingID, Cost, getCopyMapping(DstRB.getID(), SrcRB.getID(), DstSize), in getInstrMapping()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 803 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectTruncOrPtrToInt() local
805 if (DstRB.getID() != SrcRB.getID()) { in selectTruncOrPtrToInt()
812 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); in selectTruncOrPtrToInt()
932 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectAnyext() local
934 assert(DstRB.getID() == SrcRB.getID() && in selectAnyext()
941 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); in selectAnyext()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 2200 const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_TRUNC() local
2205 DstRB = SrcRB; in selectG_TRUNC()
2208 if (SrcRB != DstRB) in selectG_TRUNC()
2218 TRI.getRegClassForSizeOnBank(SrcSize, *SrcRB); in selectG_TRUNC()
2906 const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_PTRMASK() local
2909 if (DstRB != SrcRB) // Should only happen for hand written MIR. in selectG_PTRMASK()
2936 const TargetRegisterClass *SrcRC = TRI.getRegClassForTypeOnBank(Ty, *SrcRB); in selectG_PTRMASK()
3045 const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_EXTRACT_VECTOR_ELT() local
3054 TRI.getRegClassForTypeOnBank(SrcTy, *SrcRB); in selectG_EXTRACT_VECTOR_ELT()
3072 if (SrcRB->getID() == AMDGPU::SGPRRegBankID) { in selectG_EXTRACT_VECTOR_ELT()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineVerifier.cpp | 1161 const RegisterBank *SrcRB = RBI->getRegBank(Src, *MRI, *TRI); in verifyPreISelGenericInstruction() local
1165 if ((SrcRB && DstRB && SrcRB != DstRB) || (DstRB && !SrcRB)) { in verifyPreISelGenericInstruction()
|