| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTfrCleanup.cpp | 204 unsigned SrcR = MI->getOperand(1).getReg(); in rewriteIfImm() local
206 if (!isIntReg(DstR, Is32) || !isIntReg(SrcR, Tmp)) in rewriteIfImm()
210 bool Found = getReg(SrcR, Val, IMap); in rewriteIfImm()
244 unsigned DefR, SrcR; in eraseIfRedundant() local
250 SrcR = MI->getOperand(1).getReg(); in eraseIfRedundant()
257 SrcR = MI->getOperand(2).getReg(); in eraseIfRedundant()
263 if (DefR != SrcR) in eraseIfRedundant()
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| H A D | HexagonGenInsert.cpp | 468 : SrcR(SR), InsR(IR), Wdh(W), Off(O) {} in IFRecord()
470 unsigned SrcR, InsR; member
486 unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR; in operator <<() local
487 OS << '(' << printReg(SrcR, P.TRI) << ',' << printReg(InsR, P.TRI) in operator <<()
533 bool isValidInsertForm(unsigned DstR, unsigned SrcR, unsigned InsR,
674 bool HexagonGenInsert::isValidInsertForm(unsigned DstR, unsigned SrcR, in isValidInsertForm() argument
677 const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcR); in isValidInsertForm()
864 for (unsigned SrcR : AVs) { in findRecordInsertForms() local
866 const BitTracker::RegisterCell &AC = CMS->lookup(SrcR); in findRecordInsertForms()
899 if (!isValidInsertForm(VR, SrcR, InsR, L, S)) in findRecordInsertForms()
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| H A D | RDFCopy.cpp | 47 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg()); in interpretAsCopy() local
49 assert(Register::isPhysicalRegister(SrcR.Reg)); in interpretAsCopy()
52 TRI.getMinimalPhysRegClass(SrcR.Reg)) in interpretAsCopy()
54 if (!DFG.isTracked(SrcR) || !DFG.isTracked(DstR)) in interpretAsCopy()
56 EM.insert(std::make_pair(DstR, SrcR)); in interpretAsCopy()
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| H A D | HexagonRDFOpt.cpp | 118 auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { in INITIALIZE_PASS_DEPENDENCY() argument
119 EM.insert(std::make_pair(DstR, SrcR)); in INITIALIZE_PASS_DEPENDENCY()
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| H A D | HexagonFrameLowering.cpp | 1724 Register SrcR = MI->getOperand(1).getReg(); in expandCopy() local
1726 !Hexagon::ModRegsRegClass.contains(SrcR)) in expandCopy()
1748 Register SrcR = MI->getOperand(2).getReg(); in expandStoreInt() local
1758 .addReg(SrcR, getKillRegState(IsKill)); in expandStoreInt()
1811 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVecPred() local
1827 .addReg(SrcR, getKillRegState(IsKill)) in expandStoreVecPred()
1898 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVec2() local
1899 Register SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo); in expandStoreVec2()
1900 Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi); in expandStoreVec2()
1987 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVec() local
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| H A D | HexagonBitSimplify.cpp | 2246 unsigned SrcR = B0.RefI.Reg; in genBitSplit() local
2255 if (V.RefI.Reg != SrcR || V.RefI.Pos != Pos+i) in genBitSplit()
2274 if (S0.Type != BitTracker::BitValue::Ref || S0.RefI.Reg != SrcR) in genBitSplit()
2291 if (V.RefI.Reg != SrcR || V.RefI.Pos != P+I) in genBitSplit()
2306 if (MRI.getRegClass(SrcR)->getID() == Hexagon::DoubleRegsRegClassID) in genBitSplit()
2308 if (!validateReg({SrcR,SrcSR}, Hexagon::A4_bitspliti, 1)) in genBitSplit()
2318 if (Op1.getReg() != SrcR || Op1.getSubReg() != SrcSR) in genBitSplit()
2337 .addReg(SrcR, 0, SrcSR) in genBitSplit()
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| H A D | HexagonConstPropagation.cpp | 1942 RegisterSubReg SrcR(MI.getOperand(1)); in evaluate() local
1943 bool Eval = evaluateCOPY(SrcR, Inputs, RC); in evaluate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FixupLEAs.cpp | 726 const MachineOperand &SrcR = SrcR1 == DstR ? Base : Index; in processInstructionForSlowLEA()
728 .add(SrcR) in processInstructionForSlowLEA()
725 const MachineOperand &SrcR = SrcR1 == DstR ? Base : Index; processInstructionForSlowLEA() local
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