| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CSEMIRBuilder.cpp | 114 ArrayRef<SrcOp> SrcOps, in profileEverything() argument
122 profileSrcOps(SrcOps, B); in profileEverything()
177 ArrayRef<SrcOp> SrcOps, in buildInstr() argument
183 assert(SrcOps.size() == 3 && "Invalid sources"); in buildInstr()
185 LLT SrcTy = SrcOps[1].getLLTTy(*getMRI()); in buildInstr()
188 ConstantFoldICmp(SrcOps[0].getPredicate(), SrcOps[1].getReg(), in buildInstr()
189 SrcOps[2].getReg(), *getMRI())) { in buildInstr()
215 assert(SrcOps.size() == 2 && "Invalid sources"); in buildInstr()
217 LLT SrcTy = SrcOps[0].getLLTTy(*getMRI()); in buildInstr()
226 Opc, SrcOps[0].getReg(), SrcOps[1].getReg(), *getMRI()); in buildInstr()
[all …]
|
| H A D | MachineIRBuilder.cpp | 673 ArrayRef<SrcOp> SrcOps) const { in getOpcodeForMerge()
675 if (SrcOps[0].getLLTTy(*getMRI()).isVector()) in getOpcodeForMerge()
1200 ArrayRef<SrcOp> SrcOps, in buildInstr() argument
1207 assert(SrcOps.size() == 3 && "Invalid select"); in buildInstr()
1209 DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()), in buildInstr()
1210 SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI())); in buildInstr()
1217 assert(SrcOps.size() == 1 && "Invalid Srcs"); in buildInstr()
1219 SrcOps[0].getLLTTy(*getMRI())); in buildInstr()
1241 assert(SrcOps.size() == 2 && "Invalid Srcs"); in buildInstr()
1243 SrcOps[0].getLLTTy(*getMRI()), in buildInstr()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CSEMIRBuilder.h | 73 ArrayRef<SrcOp> SrcOps, std::optional<unsigned> Flags,
95 buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps, ArrayRef<SrcOp> SrcOps,
|
| H A D | MachineIRBuilder.h | 228 unsigned getOpcodeForMerge(const DstOp &DstOp, ArrayRef<SrcOp> SrcOps) const;
2242 buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps, ArrayRef<SrcOp> SrcOps,
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 75 SmallVector<SrcOp, 2> SrcOps; ///< Source registers. member
77 std::initializer_list<SrcOp> SrcOps) in ShuffleVectorPseudo()
78 : Opc(Opc), Dst(Dst), SrcOps(SrcOps){}; in ShuffleVectorPseudo()
384 MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst}, MatchInfo.SrcOps); in applyShuffleVectorPseudo()
393 if (MatchInfo.SrcOps[2].getImm() == 0) in applyEXT()
394 MIRBuilder.buildCopy(MatchInfo.Dst, MatchInfo.SrcOps[0]); in applyEXT()
398 MIRBuilder.buildConstant(LLT::scalar(32), MatchInfo.SrcOps[2].getImm()); in applyEXT()
400 {MatchInfo.SrcOps[0], MatchInfo.SrcOps[1], Cst}); in applyEXT()
|
| H A D | AArch64InstructionSelector.cpp | 262 std::initializer_list<llvm::SrcOp> SrcOps,
4252 std::initializer_list<llvm::SrcOp> SrcOps, MachineIRBuilder &MIRBuilder, in emitInstr() argument
4257 auto MI = MIRBuilder.buildInstr(Opcode, DstOps, SrcOps); in emitInstr()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 4298 SmallVector<SDValue> SrcOps(Ops.begin(), Ops.end()); in getAVX512Node() local
4299 for (SDValue &Op : SrcOps) { in getAVX512Node()
4316 SDValue Res = DAG.getNode(Opcode, DL, DstVT, SrcOps); in getAVX512Node()
22220 SmallVectorImpl<SDValue> &SrcOps, in matchScalarReduction() argument
22263 SrcOps.push_back(Src); in matchScalarReduction()
22275 for (SDValue &SrcOp : SrcOps) in matchScalarReduction()
39700 ArrayRef<SDValue> SrcOps, int SrcOpIndex, SDValue Root, in combineX86ShufflesRecursively() argument
39719 SDValue Op = SrcOps[SrcOpIndex]; in combineX86ShufflesRecursively()
39832 Ops.append(SrcOps.begin(), SrcOps.end()); in combineX86ShufflesRecursively()
49883 SmallVector<SDValue, 2> SrcOps; in combineAnd() local
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 24032 SmallVector<SDValue, 4> SrcOps; in combineConcatVectorOfCasts() local
24037 SrcOps.push_back(Op.getOperand(0)); in combineConcatVectorOfCasts()
24067 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, DL, ConcatSrcVT, SrcOps); in combineConcatVectorOfCasts()
|