Searched refs:SrcOp1 (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | AsmMatcherEmitter.cpp | 1871 unsigned SrcOp1 = 0; in buildAliasResultOperands() local
1878 SrcOp1 = ResOperands[TiedOp].AsmOperandNum; in buildAliasResultOperands()
1881 StringRef Name = AsmOperands[SrcOp1].SrcOpName; in buildAliasResultOperands()
1882 auto Insert = OperandRefs.try_emplace(Name, SrcOp1); in buildAliasResultOperands()
1892 SrcOp2 = (SrcOp2 == (unsigned)-1) ? SrcOp1 : SrcOp2; in buildAliasResultOperands()
1901 SrcOp1 = ResOperands[TiedOp].AsmOperandNum; in buildAliasResultOperands()
1906 ResOperand::getTiedOp((unsigned)-1, SrcOp1, SrcOp2)); in buildAliasResultOperands()
1908 ResOperands.push_back(ResOperand::getTiedOp(TiedOp, SrcOp1, SrcOp2)); in buildAliasResultOperands()
2193 uint8_t SrcOp1 = OpInfo.TiedOperands.SrcOpnd1Idx + HasMnemonicFirst; in emitConvertFuncs() local
2198 utostr(SrcOp1) + '_' + utostr(SrcOp2); in emitConvertFuncs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86MCInstLower.cpp | 1527 const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx); in getShuffleComment() local
1529 StringRef Src1Name = SrcOp1.isReg() in getShuffleComment()
1530 ? X86ATTInstPrinter::getRegisterName(SrcOp1.getReg()) in getShuffleComment()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 27814 auto SrcOp1 = Op.getOperand(0); in LowerFixedLengthConcatVectorsToSVE() local
27817 EVT SrcVT = SrcOp1.getValueType(); in LowerFixedLengthConcatVectorsToSVE()
27832 SrcOp1 = convertToScalableVector(DAG, ContainerVT, SrcOp1); in LowerFixedLengthConcatVectorsToSVE()
27835 Op = DAG.getNode(AArch64ISD::SPLICE, DL, ContainerVT, Pg, SrcOp1, SrcOp2); in LowerFixedLengthConcatVectorsToSVE()
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