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Searched refs:SrcMask (Results 1 – 6 of 6) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVPlanPredicator.cpp96 VPValue *SrcMask = getBlockInMask(Src); in createEdgeMask() local
100 return setEdgeMask(Src, Dst, SrcMask); in createEdgeMask()
111 return setEdgeMask(Src, Dst, SrcMask); in createEdgeMask()
119 if (SrcMask) { // Otherwise block in-mask is all-one, no need to AND. in createEdgeMask()
123 EdgeMask = Builder.createLogicalAnd(SrcMask, EdgeMask, Term->getDebugLoc()); in createEdgeMask()
202 VPValue *SrcMask = getBlockInMask(Src); in createSwitchEdgeMasks() local
211 if (SrcMask) in createSwitchEdgeMasks()
212 Mask = Builder.createLogicalAnd(SrcMask, Mask); in createSwitchEdgeMasks()
224 if (SrcMask) in createSwitchEdgeMasks()
225 DefaultMask = Builder.createLogicalAnd(SrcMask, DefaultMask); in createSwitchEdgeMasks()
H A DVectorCombine.cpp727 SmallVector<int> SrcMask; in foldInsExtFNeg() local
729 SrcMask.assign(NumElts, PoisonMaskElem); in foldInsExtFNeg()
730 SrcMask[Index] = Index; in foldInsExtFNeg()
732 VecTy, SrcVecTy, SrcMask, CostKind); in foldInsExtFNeg()
743 Value *LenChgShuf = Builder.CreateShuffleVector(VecFNeg, SrcMask); in foldInsExtFNeg()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp1549 LaneBitmask SrcMask = LaneBitmask::getLane(SrcBit); in computeSubRegLaneMasks() local
1552 assert(Idx2.LaneMask == SrcMask); in computeSubRegLaneMasks()
1569 I.Mask |= SrcMask; in computeSubRegLaneMasks()
1570 SrcMask = LaneBitmask::getNone(); in computeSubRegLaneMasks()
1573 if (SrcMask.any()) { in computeSubRegLaneMasks()
1574 MaskRolPair MaskRol = {SrcMask, RotateLeft}; in computeSubRegLaneMasks()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/
H A DMemorySanitizer.cpp3722 Value *findDppPoisonedOutput(IRBuilder<> &IRB, Value *S, unsigned SrcMask, in findDppPoisonedOutput()
3727 S = IRB.CreateSelect(createDppMask(Width, SrcMask), S, in findDppPoisonedOutput()
3760 const unsigned SrcMask = Mask >> 4; in handleDppIntrinsic() local
3764 Value *SI1 = findDppPoisonedOutput(IRB, S, SrcMask, DstMask); in handleDppIntrinsic()
3769 SI1, findDppPoisonedOutput(IRB, S, SrcMask << 4, DstMask << 4)); in handleDppIntrinsic()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterCoalescer.cpp1747 LaneBitmask SrcMask = TRI->getSubRegIndexLaneMask(SrcSubIdx); in eliminateUndefCopy() local
1749 if ((SR.LaneMask & SrcMask).none()) in eliminateUndefCopy()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp3958 static void growShuffleMask(ArrayRef<int> SrcMask, in growShuffleMask() argument
3964 unsigned NumSrcElts = SrcMask.size(); in growShuffleMask()
3965 DstMask.assign(SrcMask.begin(), SrcMask.end()); in growShuffleMask()
22957 SmallVectorImpl<APInt> *SrcMask = nullptr) { in matchScalarReduction() argument
23009 if (SrcMask) { in matchScalarReduction()
23012 SrcMask->push_back(SrcOpMap[SrcOp]); in matchScalarReduction()
23272 APInt SrcMask = APInt::getAllOnes(LHSVT.getScalarSizeInBits()); in MatchVectorAllEqualTest() local
23273 return LowerVectorAllEqual(DL, LHS, RHS, CC, SrcMask, Subtarget, DAG, in MatchVectorAllEqualTest()
23285 APInt SrcMask = APInt(BW, 1); in MatchVectorAllEqualTest() local
23286 APInt Cmp = CmpNull ? APInt::getZero(BW) : SrcMask; in MatchVectorAllEqualTest()
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