Searched refs:SrcLo (Results 1 – 7 of 7) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRInstrInfo.cpp | 56 Register DestLo, DestHi, SrcLo, SrcHi; in copyPhysReg() local
59 TRI.splitReg(SrcReg, SrcLo, SrcHi); in copyPhysReg()
70 .addReg(SrcLo, getKillRegState(KillSrc) | RegState::Undef); in copyPhysReg()
73 .addReg(SrcLo, getKillRegState(KillSrc) | RegState::Undef); in copyPhysReg()
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| H A D | AVRISelLowering.cpp | 279 SDValue SrcLo = in LowerShifts() local
294 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i32, Zero, SrcLo); in LowerShifts()
317 SDValue Result = DAG.getNode(Opc, dl, ResTys, SrcLo, SrcHi, Cnt); in LowerShifts()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 709 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); in expandPseudoMTLoHi() local
723 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill())); in expandPseudoMTLoHi()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 924 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in copyPhysReg() local
926 unsigned UndefLo = getUndefRegState(!LiveAtMI.contains(SrcLo)); in copyPhysReg()
930 .addReg(SrcLo, KillFlag | UndefLo); in copyPhysReg()
1141 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in expandPostRAPseudo() local
1144 unsigned UndefLo = getUndefRegState(!LiveIn.contains(SrcLo)); in expandPostRAPseudo()
1149 .addReg(SrcLo, Kill | UndefLo); in expandPostRAPseudo()
1411 Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo); in expandPostRAPseudo() local
1417 .addReg(SrcLo); in expandPostRAPseudo()
1423 Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo); in expandPostRAPseudo() local
1429 .addReg(SrcLo); in expandPostRAPseudo()
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| H A D | HexagonFrameLowering.cpp | 1899 Register SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo); in expandStoreVec2() local
1910 if (LPR.contains(SrcLo)) { in expandStoreVec2()
1916 .addReg(SrcLo, getKillRegState(IsKill)) in expandStoreVec2()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 3006 SDValue SrcLo, SrcHi; in SplitVecRes_FP_TO_XINT_SAT()
3009 GetSplitVector(N->getOperand(0), SrcLo, SrcHi); in SplitVecRes_FP_TO_XINT_SAT()
3011 std::tie(SrcLo, SrcHi) = DAG.SplitVectorOperand(N, 0); in SplitVecRes_FP_TO_XINT_SAT()
3013 Lo = DAG.getNode(N->getOpcode(), dl, DstVTLo, SrcLo, N->getOperand(1)); in SplitVecRes_VECTOR_REVERSE()
3002 SDValue SrcLo, SrcHi; SplitVecRes_FP_TO_XINT_SAT() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 4809 SDValue SrcLo = DAG.getNode(ISD::AND, DL, MVT::i64, SrcVal, in LowerINT_TO_FP() local
4835 SrcLo, Zero64, ISD::SETNE); in LowerINT_TO_FP()
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