| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRInstrInfo.cpp | 56 Register DestLo, DestHi, SrcLo, SrcHi; in copyPhysReg() local
59 TRI.splitReg(SrcReg, SrcLo, SrcHi); in copyPhysReg()
66 if (DestLo == SrcHi) { in copyPhysReg()
68 .addReg(SrcHi, getKillRegState(KillSrc) | RegState::Undef); in copyPhysReg()
75 .addReg(SrcHi, getKillRegState(KillSrc) | RegState::Undef); in copyPhysReg()
|
| H A D | AVRISelLowering.cpp | 282 SDValue SrcHi = in LowerShifts() local
298 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i32, SrcHi, Zero); in LowerShifts()
317 SDValue Result = DAG.getNode(Opc, dl, ResTys, SrcLo, SrcHi, Cnt); in LowerShifts()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 709 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); in expandPseudoMTLoHi() local
724 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill())); in expandPseudoMTLoHi()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 925 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in copyPhysReg() local
927 unsigned UndefHi = getUndefRegState(!LiveAtMI.contains(SrcHi)); in copyPhysReg()
929 .addReg(SrcHi, KillFlag | UndefHi) in copyPhysReg()
1142 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in expandPostRAPseudo() local
1145 unsigned UndefHi = getUndefRegState(!LiveIn.contains(SrcHi)); in expandPostRAPseudo()
1148 .addReg(SrcHi, UndefHi) in expandPostRAPseudo()
1412 Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo() local
1416 .addReg(SrcHi) in expandPostRAPseudo()
1424 Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo() local
1428 .addReg(SrcHi) in expandPostRAPseudo()
|
| H A D | HexagonFrameLowering.cpp | 1900 Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi); in expandStoreVec2() local
1921 if (LPR.contains(SrcHi)) { in expandStoreVec2()
1927 .addReg(SrcHi, getKillRegState(IsKill)) in expandStoreVec2()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 3002 SDValue SrcLo, SrcHi; in SplitVecRes_FP_TO_XINT_SAT() local
3005 GetSplitVector(N->getOperand(0), SrcLo, SrcHi); in SplitVecRes_FP_TO_XINT_SAT()
3007 std::tie(SrcLo, SrcHi) = DAG.SplitVectorOperand(N, 0); in SplitVecRes_FP_TO_XINT_SAT()
3010 Hi = DAG.getNode(N->getOpcode(), dl, DstVTHi, SrcHi, N->getOperand(1)); in SplitVecRes_FP_TO_XINT_SAT()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 8708 SDValue SrcHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, SrcVec, in LowerINTRINSIC_WO_CHAIN() local
8710 return DAG.getSetCC(SL, MVT::i1, SrcHi, Aperture, ISD::SETEQ); in LowerINTRINSIC_WO_CHAIN()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 4807 SDValue SrcHi = DAG.getNode(ISD::AND, DL, MVT::i64, SrcVal, in LowerINT_TO_FP() local
4816 DAG.getSelectCC(DL, Highest, Zero64, SrcHi, SrcVal, ISD::SETNE); in LowerINT_TO_FP()
|