Searched refs:SrcElt (Results 1 – 7 of 7) sorted by relevance
1608 Register SrcElt = Def->getOperand(I).getReg(); in matchUnaryPredicate() local1609 const MachineInstr *SrcDef = getDefIgnoringCopies(SrcElt, MRI); in matchUnaryPredicate()
1570 unsigned SrcElt = 0; in executeBitCastInst() local1579 Tmp = TempSrc.AggregateVal[SrcElt++].IntVal; in executeBitCastInst()
10745 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i]; in LowerVPERM() local10748 if (SrcElt < 8) in LowerVPERM()10749 SrcElt += 8; in LowerVPERM()10750 else if (SrcElt < 16) in LowerVPERM()10751 SrcElt -= 8; in LowerVPERM()10754 if (SrcElt > 23) in LowerVPERM()10755 SrcElt -= 8; in LowerVPERM()10756 else if (SrcElt > 15) in LowerVPERM()10757 SrcElt += 8; in LowerVPERM()10760 if (SrcElt < 16) in LowerVPERM()[all …]
227 unsigned SrcElt = 0; in FoldBitCast() local233 Constant *Src = C->getAggregateElement(SrcElt++); in FoldBitCast()
3326 for (unsigned SrcElt = 0; SrcElt != NumSrcElts; ++SrcElt) { in SimplifyDemandedVectorElts() local3327 unsigned Elt = Scale * SrcElt + SubElt; in SimplifyDemandedVectorElts()
26423 for (unsigned SrcElt = 0, NumSrcElts = NumElts / Scale; in combineShuffleToZeroExtendVectorInReg() local26424 SrcElt != NumSrcElts; ++SrcElt) { in combineShuffleToZeroExtendVectorInReg()26431 if (int FirstIndice = MaskChunk[0]; (unsigned)FirstIndice != SrcElt) in combineShuffleToZeroExtendVectorInReg()
4404 SDValue SrcElt = in performTruncateCombine() local4407 return DAG.getNode(ISD::TRUNCATE, SL, VT, SrcElt); in performTruncateCombine()