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Searched refs:Src2Reg (Results 1 – 12 of 12) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZPostRewrite.cpp105 Register Src2Reg = MBBI->getOperand(2).getReg(); in selectSELRMux() local
108 bool Src2IsHigh = SystemZ::isHighReg(Src2Reg); in selectSELRMux()
113 if (DestReg != Src1Reg && DestReg != Src2Reg) { in selectSELRMux()
126 Src2Reg = DestReg; in selectSELRMux()
132 if (DestReg != Src1Reg && DestReg == Src2Reg) { in selectSELRMux()
134 std::swap(Src1Reg, Src2Reg); in selectSELRMux()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp190 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
319 Src2Reg = MCI.getOperand(2).getReg(); in getDuplexCandidateGroup()
321 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) && in getDuplexCandidateGroup()
327 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) && in getDuplexCandidateGroup()
335 Src2Reg = MCI.getOperand(2).getReg(); in getDuplexCandidateGroup()
337 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) && in getDuplexCandidateGroup()
354 Src2Reg = MCI.getOperand(2).getReg(); in getDuplexCandidateGroup()
356 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) && in getDuplexCandidateGroup()
364 Src2Reg = MCI.getOperand(2).getReg(); in getDuplexCandidateGroup()
365 if (HexagonMCInstrInfo::isDblRegForSubInst(Src2Reg) && in getDuplexCandidateGroup()
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H A DHexagonMCCompound.cpp81 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
99 Src2Reg = MI.getOperand(2).getReg(); in getCompoundCandidateGroup()
102 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg)) in getCompoundCandidateGroup()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1289 Register Src2Reg = MI.getOperand(2).getReg(); in expandPostRAPseudo() local
1292 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi); in expandPostRAPseudo()
1293 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo); in expandPostRAPseudo()
1313 Register Src2Reg = MI.getOperand(2).getReg(); in expandPostRAPseudo() local
1317 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi); in expandPostRAPseudo()
1318 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo); in expandPostRAPseudo()
3427 Register DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
3443 Src2Reg = MI.getOperand(2).getReg(); in getCompoundCandidateGroup()
3446 isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg)) in getCompoundCandidateGroup()
3925 Register DstReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp276 Register Src2Reg = MI->getOperand(3).getReg(); in ExpandFPMLxInstruction() local
292 .addReg(Src2Reg, getKillRegState(Src2Kill)); in ExpandFPMLxInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp2660 Register Src2Reg = getRegForValue(Src2Val); in optimizeSelect() local
2661 if (!Src2Reg) in optimizeSelect()
2668 Src2Reg); in optimizeSelect()
2780 Register Src2Reg = getRegForValue(SI->getFalseValue()); in selectSelect() local
2782 if (!Src1Reg || !Src2Reg) in selectSelect()
2786 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src2Reg, ExtraCC); in selectSelect()
2788 Register ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src2Reg, CC); in selectSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1039 Register Src2Reg = getRegForValue(SI->getFalseValue()); in selectSelect() local
1042 if (!Src1Reg || !Src2Reg || !CondReg) in selectSelect()
1058 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg); in selectSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp1897 Register Src2Reg = I.getOperand(2).getReg(); in selectVectorSHL() local
1904 std::optional<int64_t> ImmVal = getVectorSHLImm(Ty, Src2Reg, MRI); in selectVectorSHL()
1930 Shl.addUse(Src2Reg); in selectVectorSHL()
1943 Register Src2Reg = I.getOperand(2).getReg(); in selectVectorAshrLshr() local
1987 auto Neg = MIB.buildInstr(NegOpc, {RC}, {Src2Reg}); in selectVectorAshrLshr()
3802 Register Src2Reg = I.getOperand(2).getReg(); in selectMergeValues() local
3809 Src2Reg, /* LaneIdx */ 1, RB, MIB); in selectMergeValues()
5067 Register Src2Reg = I.getOperand(2).getReg(); in selectShuffleVector() local
5068 const LLT Src2Ty = MRI.getType(Src2Reg); in selectShuffleVector()
5108 emitVectorConcat(std::nullopt, Src1Reg, Src2Reg, MIB); in selectShuffleVector()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp4679 Register Src2Reg = PtrAdd.getOffsetReg(); in reassociationCanBreakAddressingModePattern() local
4687 auto C2 = getIConstantVRegVal(Src2Reg, MRI); in reassociationCanBreakAddressingModePattern()
4799 Register Src2Reg = MI.getOperand(2).getReg(); in matchReassocFoldConstantsInSubTree() local
4805 auto C2 = getIConstantVRegVal(Src2Reg, MRI); in matchReassocFoldConstantsInSubTree()
4810 auto NewCst = B.buildConstant(MRI.getType(Src2Reg), *C1 + *C2); in matchReassocFoldConstantsInSubTree()
H A DLegalizerHelper.cpp4911 auto [DstReg, DstTy, Src1Reg, Src1Ty, Src2Reg, Src2Ty] = in fewerElementsVectorShuffle()
4931 extractParts(Src2Reg, NarrowTy, 2, SplitSrc2Regs, MIRBuilder, MRI); in fewerElementsVectorShuffle()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp4144 MCRegister Src2Reg = Src2.getReg(); in validateMFMA() local
4146 if (Src2Reg == DstReg) in validateMFMA()
4153 if (TRI->regsOverlap(Src2Reg, DstReg)) { in validateMFMA()
4154 Error(getRegLoc(mc2PseudoReg(Src2Reg), Operands), in validateMFMA()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp18259 Register Src2Reg = MI.getOperand(2).getReg(); in emitQuietFCMP()
18269 .addReg(Src2Reg); in emitQuietFCMP()
18280 .addReg(Src2Reg, getKillRegState(MI.getOperand(2).isKill())); in emitQuietFCMP()
18256 Register Src2Reg = MI.getOperand(2).getReg(); emitQuietFCMP() local