Home
last modified time | relevance | path

Searched refs:Src2 (Results 1 – 25 of 55) sorted by relevance

123

/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp105 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
109 GenericValue Src2, Type *Ty) { in executeFAddInst() argument
120 GenericValue Src2, Type *Ty) { in executeFSubInst() argument
131 GenericValue Src2, Type *Ty) { in executeFMulInst() argument
142 GenericValue Src2, Type *Ty) { in executeFDivInst() argument
153 GenericValue Src2, Type *Ty) { in executeFRemInst() argument
156 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal); in executeFRemInst()
159 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal); in executeFRemInst()
169 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
175 assert(Src1.AggregateVal.size() == Src2.AggregateVal.size()); \
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURewriteAGPRCopyMFMA.cpp144 MachineOperand *Src2 = in run() local
152 Register Src2PhysReg = VRM.getPhys(Src2->getReg()); in run()
156 << printReg(Src2->getReg(), &TRI) << " => " in run()
162 if (Src2->getReg() != CopySrcReg) { in run()
177 MRI.getRegClass(Src2->getReg()); in run()
186 Src2->getReg(), Src2VirtRegRC, VirtRegRC, CopySrcMI); in run()
191 TII.getRegClass(TII.get(AGPROp), Src2->getOperandNo(), &TRI, MF); in run()
200 LLVM_DEBUG(dbgs() << "Other uses of " << printReg(Src2->getReg(), &TRI) in run()
206 MRI.setRegClass(Src2->getReg(), NewSrc2RC); in run()
H A DGCNVOPDUtils.cpp167 const MachineOperand &Src2 = in checkVOPDRegConstraints() local
169 if (!Src2.isImm() || Src2.getImm()) in checkVOPDRegConstraints()
173 const MachineOperand &Src2 = in checkVOPDRegConstraints() local
175 if (!Src2.isImm() || Src2.getImm()) in checkVOPDRegConstraints()
H A DAMDGPUMacroFusion.cpp46 const MachineOperand *Src2 = TII.getNamedOperand(SecondMI, in shouldScheduleAdjacent() local
48 return FirstMI->definesRegister(Src2->getReg(), TRI); in shouldScheduleAdjacent()
H A DAMDGPUCombinerHelper.h39 Register Src1, Register Src2) const;
41 Register Src1, Register Src2) const;
H A DSIShrinkInstructions.cpp430 MachineOperand &Src2 = *TII->getNamedOperand(MI, AMDGPU::OpName::src2); in shrinkMadFma() local
436 if (Src2.isImm() && !TII->isInlineConstant(Src2)) { in shrinkMadFma()
474 if (Src2.isReg() && TRI->isVGPR(*MRI, Src2.getReg())) { in shrinkMadFma()
523 .add(Src2) in shrinkMadFma()
1027 const MachineOperand *Src2 = in run() local
1029 if (!Src2->isReg()) in run()
1031 Register SReg = Src2->getReg(); in run()
1055 const MachineOperand *Src2 = TII->getNamedOperand(MI, in run() local
1057 if (Src2 && Src2->getReg() != VCCReg) { in run()
1058 if (Src2->getReg().isVirtual()) in run()
[all …]
H A DAMDGPUInstCombineIntrinsic.cpp47 const APFloat &Src2) { in fmed3AMDGCN() argument
48 APFloat Max3 = maxnum(maxnum(Src0, Src1), Src2); in fmed3AMDGCN()
53 return maxnum(Src1, Src2); in fmed3AMDGCN()
58 return maxnum(Src0, Src2); in fmed3AMDGCN()
1003 Value *Src2 = II.getArgOperand(2); in instCombineIntrinsic() local
1005 for (Value *Src : {Src0, Src1, Src2}) { in instCombineIntrinsic()
1059 return IC.replaceInstUsesWith(II, Src2); in instCombineIntrinsic()
1061 V = IsPosInfinity ? IC.Builder.CreateMaxNum(Src1, Src2) in instCombineIntrinsic()
1062 : IC.Builder.CreateMinNum(Src1, Src2); in instCombineIntrinsic()
1065 V = IsPosInfinity ? IC.Builder.CreateMaximumNum(Src1, Src2) in instCombineIntrinsic()
[all …]
H A DGCNDPPCombine.cpp350 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); in createDPPInst() local
351 if (Src2) { in createDPPInst()
353 !TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) { in createDPPInst()
358 DPPInst.add(*Src2); in createDPPInst()
402 assert(Src2 && "Expected vop3p with 3 operands"); in createDPPInst()
694 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); in combineDPPMov() local
697 (Src2 && Src2->isIdenticalTo(*Src0)))) || in combineDPPMov()
699 (Src2 && Src2->isIdenticalTo(*Src1))))) { in combineDPPMov()
H A DAMDGPUCombinerHelper.cpp428 Register Src2) const { in matchExpandPromotedF16FMed3()
435 isFPExtFromF16OrConst(MRI, Src2); in matchExpandPromotedF16FMed3()
441 Register Src2) const { in applyExpandPromotedF16FMed3()
446 Src2 = Builder.buildFPTrunc(LLT::scalar(16), Src2).getReg(0); in applyExpandPromotedF16FMed3()
451 auto C1 = Builder.buildFMaxNumIEEE(Ty, A1, Src2); in applyExpandPromotedF16FMed3()
H A DSIOptimizeExecMasking.cpp165 const MachineOperand &Src2 = MI.getOperand(2); in isLogicalOpOnExec() local
166 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
181 const MachineOperand &Src2 = MI.getOperand(2); in isLogicalOpOnExec() local
182 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
H A DAMDGPURegBankCombiner.cpp318 MachineInstr *Src2 = getDefIgnoringCopies(MI.getOperand(3).getReg(), MRI); in matchFPMed3ToClamp() local
322 if (isFCst(Src1) && !isFCst(Src2)) in matchFPMed3ToClamp()
323 std::swap(Src1, Src2); in matchFPMed3ToClamp()
326 if (!isClampZeroToOne(Src1, Src2)) in matchFPMed3ToClamp()
H A DSIPeepholeSDWA.cpp795 MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); in matchSDWAOperand() local
796 auto Width = foldToImm(*Src2); in matchSDWAOperand()
1256 MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); in createSDWAVersion() local
1257 assert(Src2); in createSDWAVersion()
1258 SDWAInst.add(*Src2); in createSDWAVersion()
H A DSIInstrInfo.cpp3649 MachineOperand *Src2 = getNamedOperand(UseMI, AMDGPU::OpName::src2); in foldImmediate() local
3662 if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))) in foldImmediate()
3673 MachineInstr *Def = MRI->getUniqueVRegDef(Src2->getReg()); in foldImmediate()
3721 if (Src2->isReg() && Src2->getReg() == Reg) { in foldImmediate()
3778 extractSubregFromImm(Imm, Src2->getSubReg()); in foldImmediate()
3781 Src2->ChangeToImmediate(*SubRegImm); in foldImmediate()
4087 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2); in convertToThreeAddress() local
4135 if (!Src0Literal && getFoldableImm(Src2, Imm, &DefMI)) { in convertToThreeAddress()
4158 .add(*Src2) in convertToThreeAddress()
4181 .add(*Src2) in convertToThreeAddress()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp127 const MachineOperand &Src2) const;
198 const MachineOperand &Src2) const { in getMuxOpcode()
199 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg(); in getMuxOpcode()
207 if (Src2.isImm() && isInt<8>(Src2.getImm())) in getMuxOpcode()
290 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); in genMuxInBlock() local
292 Register SR2 = Src2->isReg() ? Src2->getReg() : Register(); in genMuxInBlock()
308 MachineOperand *SrcT = (MinX == CI.TrueX) ? Src1 : Src2; in genMuxInBlock()
309 MachineOperand *SrcF = (MinX == CI.FalseX) ? Src1 : Src2; in genMuxInBlock()
H A DHexagonPeephole.cpp141 MachineOperand &Src2 = MI.getOperand(2); in runOnMachineFunction() local
145 Register SrcReg = Src2.getReg(); in runOnMachineFunction()
158 MachineOperand &Src2 = MI.getOperand(2); in runOnMachineFunction() local
159 if (Src2.getImm() != 32) in runOnMachineFunction()
H A DHexagonConstPropagation.cpp1864 const MachineOperand &Src2, const CellMap &Inputs, bool &Result);
2577 const MachineOperand &Src2 = MI.getOperand(2); in evaluateHexCompare() local
2581 bool Computed = evaluateHexCompare2(Opc, Src1, Src2, Inputs, Result); in evaluateHexCompare()
2599 const MachineOperand &Src1, const MachineOperand &Src2, in evaluateHexCompare2() argument
2602 bool Reg1 = Src1.isReg(), Reg2 = Src2.isReg(); in evaluateHexCompare2()
2603 bool Imm1 = Src1.isImm(), Imm2 = Src2.isImm(); in evaluateHexCompare2()
2607 RegSubRegPair R2(getRegSubRegPair(Src2)); in evaluateHexCompare2()
2610 APInt A2 = getCmpImm(Opc, 2, Src2); in evaluateHexCompare2()
2616 RegSubRegPair R2(getRegSubRegPair(Src2)); in evaluateHexCompare2()
2620 APInt A2 = getCmpImm(Opc, 2, Src2); in evaluateHexCompare2()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.h43 SDValue Src1, SDValue Src2, SDValue Size,
59 SDValue Src1, SDValue Src2,
H A DSystemZSelectionDAGInfo.cpp184 SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo, in EmitTargetCodeForMemcmp() argument
191 CCReg = emitMemMemImm(DAG, DL, SystemZISD::CLC, Chain, Src2, Src1, Bytes); in EmitTargetCodeForMemcmp()
193 CCReg = emitMemMemReg(DAG, DL, SystemZISD::CLC, Chain, Src2, Src1, Size); in EmitTargetCodeForMemcmp()
236 SDValue Src2, MachinePointerInfo Op1PtrInfo, in EmitTargetCodeForStrcmp() argument
240 SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src2, Src1, in EmitTargetCodeForStrcmp()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMIPatternMatch.h861 Src2Ty Src2;
863 TernaryOp_match(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2)
864 : Src0(Src0), Src1(Src1), Src2(Src2) {}
872 Src2.match(MRI, TmpMI->getOperand(3).getReg()));
881 m_GInsertVecElt(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) {
883 TargetOpcode::G_INSERT_VECTOR_ELT>(Src0, Src1, Src2);
888 m_GISelect(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) {
890 Src0, Src1, Src2);
H A DMachineIRBuilder.h1176 const SrcOp &Src2, ArrayRef<int> Mask);
2062 const SrcOp &Src1, const SrcOp &Src2,
2064 return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2}, Flags);
2069 const SrcOp &Src1, const SrcOp &Src2,
2071 return buildInstr(TargetOpcode::G_FMAD, {Dst}, {Src0, Src1, Src2}, Flags);
/freebsd/sys/contrib/edk2/Include/Protocol/
H A DDevicePathUtilities.h68 IN CONST EFI_DEVICE_PATH_PROTOCOL *Src2
/freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/
H A DAMDGPU.cpp332 llvm::Value *Src2 = EmitScalarExpr(E->getArg(2)); in EmitAMDGPUBuiltinExpr() local
338 return Builder.CreateCall(F, {Src0, Src1, Src2, Src3ToBool}); in EmitAMDGPUBuiltinExpr()
509 llvm::Value *Src2 = EmitScalarExpr(E->getArg(2)); in EmitAMDGPUBuiltinExpr() local
514 return Builder.CreateCall(F, { Src0, Src1, Src2 }); in EmitAMDGPUBuiltinExpr()
520 llvm::Value *Src2 = EmitScalarExpr(E->getArg(2)); in EmitAMDGPUBuiltinExpr() local
525 return Builder.CreateCall(F, { Src0, Src1, Src2 }); in EmitAMDGPUBuiltinExpr()
1016 llvm::Value *Src2 = EmitScalarExpr(E->getArg(2)); in EmitAMDGPUBuiltinExpr() local
1018 return Builder.CreateCall(F, { Src0, Src1, Src2 }); in EmitAMDGPUBuiltinExpr()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEAsmPrinter.cpp153 MCOperand &Src2, MCOperand &RD, in emitBinary() argument
159 Inst.addOperand(Src2); in emitBinary()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcAsmPrinter.cpp140 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, in EmitBinary() argument
147 Inst.addOperand(Src2); in EmitBinary()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp1857 SDValue Src2 = Node->getOperand(2); in Select() local
1862 if (Src2.getValueType() != XLenVT) in Select()
1867 if (auto *C = dyn_cast<ConstantSDNode>(Src2)) { in Select()
1933 selectImm(CurDAG, SDLoc(Src2), XLenVT, CVal - 1, *Subtarget); in Select()
1943 CurDAG->getMachineNode(VMSLTOpcode, DL, VT, {Src1, Src2, VL, SEW}), in Select()
1952 SDValue Src2 = Node->getOperand(3); in Select() local
1957 if (Src2.getValueType() != XLenVT) in Select()
1962 if (auto *C = dyn_cast<ConstantSDNode>(Src2)) { in Select()
2044 CurDAG->getMachineNode(VMSLTOpcode, DL, VT, {Src1, Src2, VL, SEW}), in Select()
2056 selectImm(CurDAG, SDLoc(Src2), XLenVT, CVal - 1, *Subtarget); in Select()
[all …]

123