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Searched refs:Src2 (Results 1 – 25 of 48) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp105 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
109 GenericValue Src2, Type *Ty) { in executeFAddInst() argument
120 GenericValue Src2, Type *Ty) { in executeFSubInst() argument
131 GenericValue Src2, Type *Ty) { in executeFMulInst() argument
142 GenericValue Src2, Type *Ty) { in executeFDivInst() argument
153 GenericValue Src2, Type *Ty) { in executeFRemInst() argument
156 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal); in executeFRemInst()
159 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal); in executeFRemInst()
169 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
175 assert(Src1.AggregateVal.size() == Src2.AggregateVal.size()); \
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp135 const MachineOperand &Src2) const;
206 const MachineOperand &Src2) const { in getMuxOpcode()
207 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg(); in getMuxOpcode()
215 if (Src2.isImm() && isInt<8>(Src2.getImm())) in getMuxOpcode()
299 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); in genMuxInBlock() local
301 Register SR2 = Src2->isReg() ? Src2->getReg() : Register(); in genMuxInBlock()
317 MachineOperand *SrcT = (MinX == CI.TrueX) ? Src1 : Src2; in genMuxInBlock()
318 MachineOperand *SrcF = (MinX == CI.FalseX) ? Src1 : Src2; in genMuxInBlock()
H A DHexagonPeephole.cpp152 MachineOperand &Src2 = MI.getOperand(2); in runOnMachineFunction() local
156 Register SrcReg = Src2.getReg(); in runOnMachineFunction()
169 MachineOperand &Src2 = MI.getOperand(2); in runOnMachineFunction() local
170 if (Src2.getImm() != 32) in runOnMachineFunction()
H A DHexagonConstPropagation.cpp1867 const MachineOperand &Src2, const CellMap &Inputs, bool &Result);
2566 // Classic compare: Dst0 = CMP Src1, Src2 in evaluateHexCompare()
2576 const MachineOperand &Src2 = MI.getOperand(2); in evaluateHexCompare() local
2580 bool Computed = evaluateHexCompare2(Opc, Src1, Src2, Inputs, Result); in evaluateHexCompare()
2598 const MachineOperand &Src1, const MachineOperand &Src2, in evaluateHexCompare2() argument
2601 bool Reg1 = Src1.isReg(), Reg2 = Src2.isReg(); in evaluateHexCompare2()
2602 bool Imm1 = Src1.isImm(), Imm2 = Src2.isImm(); in evaluateHexCompare2()
2606 RegisterSubReg R2(Src2); in evaluateHexCompare2()
2609 APInt A2 = getCmpImm(Opc, 2, Src2); in evaluateHexCompare2()
2615 RegisterSubReg R2(Src2); in evaluateHexCompare2()
2633 const MachineOperand &Src2 = MI.getOperand(2); evaluateHexLogical() local
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCombinerHelper.h31 Register Src1, Register Src2);
33 Register Src1, Register Src2);
H A DSIShrinkInstructions.cpp420 MachineOperand &Src2 = *TII->getNamedOperand(MI, AMDGPU::OpName::src2); in shrinkMadFma() local
426 if (Src2.isImm() && !TII->isInlineConstant(Src2)) { in shrinkMadFma()
455 if (Src2.isReg() && TRI->isVGPR(*MRI, Src2.getReg())) { in shrinkMadFma()
495 .add(Src2) in shrinkMadFma()
977 const MachineOperand *Src2 = in runOnMachineFunction() local
979 if (!Src2->isReg()) in runOnMachineFunction()
981 Register SReg = Src2->getReg(); in runOnMachineFunction()
1005 const MachineOperand *Src2 = TII->getNamedOperand(MI, in runOnMachineFunction() local
1007 if (Src2 && Src2->getReg() != VCCReg) { in runOnMachineFunction()
1008 if (Src2->getReg().isVirtual()) in runOnMachineFunction()
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H A DAMDGPUMacroFusion.cpp46 const MachineOperand *Src2 = TII.getNamedOperand(SecondMI, in shouldScheduleAdjacent() local
48 return FirstMI->definesRegister(Src2->getReg(), TRI); in shouldScheduleAdjacent()
H A DAMDGPUCombinerHelper.cpp421 Register Src2) { in matchExpandPromotedF16FMed3() argument
428 isFPExtFromF16OrConst(MRI, Src2); in matchExpandPromotedF16FMed3()
434 Register Src2) { in applyExpandPromotedF16FMed3() argument
439 Src2 = Builder.buildFPTrunc(LLT::scalar(16), Src2).getReg(0); in applyExpandPromotedF16FMed3()
444 auto C1 = Builder.buildFMaxNumIEEE(Ty, A1, Src2); in applyExpandPromotedF16FMed3()
H A DGCNDPPCombine.cpp344 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); in createDPPInst() local
345 if (Src2) { in createDPPInst()
347 !TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) { in createDPPInst()
352 DPPInst.add(*Src2); in createDPPInst()
396 assert(Src2 && "Expected vop3p with 3 operands"); in createDPPInst()
691 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); in combineDPPMov() local
694 (Src2 && Src2->isIdenticalTo(*Src0)))) || in combineDPPMov()
696 (Src2 && Src2->isIdenticalTo(*Src1))))) { in combineDPPMov()
H A DAMDGPUInstCombineIntrinsic.cpp46 const APFloat &Src2) { in fmed3AMDGCN() argument
47 APFloat Max3 = maxnum(maxnum(Src0, Src1), Src2); in fmed3AMDGCN()
52 return maxnum(Src1, Src2); in fmed3AMDGCN()
57 return maxnum(Src0, Src2); in fmed3AMDGCN()
765 Value *Src2 = II.getArgOperand(2); in instCombineIntrinsic() local
772 V = IC.Builder.CreateMinNum(Src1, Src2); in instCombineIntrinsic()
774 V = IC.Builder.CreateMinNum(Src0, Src2); in instCombineIntrinsic()
775 } else if (match(Src2, PatternMatch::m_NaN()) || isa<UndefValue>(Src2)) { in instCombineIntrinsic()
796 if (isa<Constant>(Src1) && !isa<Constant>(Src2)) { in instCombineIntrinsic()
797 std::swap(Src1, Src2); in instCombineIntrinsic()
[all …]
H A DSIOptimizeExecMasking.cpp146 const MachineOperand &Src2 = MI.getOperand(2); in isLogicalOpOnExec() local
147 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
162 const MachineOperand &Src2 = MI.getOperand(2); in isLogicalOpOnExec() local
163 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
H A DAMDGPURegBankCombiner.cpp318 MachineInstr *Src2 = getDefIgnoringCopies(MI.getOperand(3).getReg(), MRI); in matchFPMed3ToClamp() local
322 if (isFCst(Src1) && !isFCst(Src2)) in matchFPMed3ToClamp()
323 std::swap(Src1, Src2); in matchFPMed3ToClamp()
326 if (!isClampZeroToOne(Src1, Src2)) in matchFPMed3ToClamp()
H A DSIPeepholeSDWA.cpp665 MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); in matchSDWAOperand() local
666 auto Width = foldToImm(*Src2); in matchSDWAOperand()
1084 MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); in convertToSDWA() local
1085 assert(Src2); in convertToSDWA()
1086 SDWAInst.add(*Src2); in convertToSDWA()
H A DSIInstrInfo.cpp3524 MachineOperand *Src2 = getNamedOperand(UseMI, AMDGPU::OpName::src2); in foldImmediate() local
3537 if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))) in foldImmediate()
3548 MachineInstr *Def = MRI->getUniqueVRegDef(Src2->getReg()); in foldImmediate()
3597 if (Src2->isReg() && Src2->getReg() == Reg) { in foldImmediate()
3656 Src2->ChangeToImmediate(getImmFor(*Src2)); in foldImmediate()
3935 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2); in convertToThreeAddress() local
3963 if (!Src0Literal && getFoldableImm(Src2, Imm, &DefMI)) { in convertToThreeAddress()
3994 .add(*Src2) in convertToThreeAddress()
4016 .add(*Src2) in convertToThreeAddress()
4051 .add(*Src2) in convertToThreeAddress()
[all …]
H A DSIISelLowering.cpp5134 MachineOperand &Src2 = MI.getOperand(4); in EmitInstrWithCustomInserter() local
5151 if (TRI->isVectorRegister(MRI, Src2.getReg())) { in EmitInstrWithCustomInserter()
5153 .addReg(Src2.getReg()); in EmitInstrWithCustomInserter()
5154 Src2.setReg(RegOp2); in EmitInstrWithCustomInserter()
5157 const TargetRegisterClass *Src2RC = MRI.getRegClass(Src2.getReg()); in EmitInstrWithCustomInserter()
5164 .addReg(Src2.getReg()) in EmitInstrWithCustomInserter()
5170 MII, MRI, Src2, Src2RC, AMDGPU::sub0, SubRC); in EmitInstrWithCustomInserter()
5172 MII, MRI, Src2, Src2RC, AMDGPU::sub1, SubRC); in EmitInstrWithCustomInserter()
5185 .addReg(Src2.getReg()) in EmitInstrWithCustomInserter()
6124 SDValue Src2, MVT ValT) -> SDValue { in lowerLaneOp() argument
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.h39 SDValue Src1, SDValue Src2, SDValue Size,
55 SDValue Src1, SDValue Src2,
H A DSystemZSelectionDAGInfo.cpp174 SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo, in EmitTargetCodeForMemcmp() argument
181 CCReg = emitMemMemImm(DAG, DL, SystemZISD::CLC, Chain, Src2, Src1, Bytes); in EmitTargetCodeForMemcmp()
183 CCReg = emitMemMemReg(DAG, DL, SystemZISD::CLC, Chain, Src2, Src1, Size); in EmitTargetCodeForMemcmp()
226 SDValue Src2, MachinePointerInfo Op1PtrInfo, in EmitTargetCodeForStrcmp() argument
230 SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src2, Src1, in EmitTargetCodeForStrcmp()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMIPatternMatch.h730 Src2Ty Src2;
732 TernaryOp_match(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2)
733 : Src0(Src0), Src1(Src1), Src2(Src2) {}
741 Src2.match(MRI, TmpMI->getOperand(3).getReg()));
750 m_GInsertVecElt(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) {
752 TargetOpcode::G_INSERT_VECTOR_ELT>(Src0, Src1, Src2);
757 m_GISelect(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) {
759 Src0, Src1, Src2);
H A DMachineIRBuilder.h1117 const SrcOp &Src2, ArrayRef<int> Mask);
1893 const SrcOp &Src1, const SrcOp &Src2,
1895 return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2}, Flags);
1900 const SrcOp &Src1, const SrcOp &Src2,
1902 return buildInstr(TargetOpcode::G_FMAD, {Dst}, {Src0, Src1, Src2}, Flags);
/freebsd/sys/contrib/edk2/Include/Protocol/
H A DDevicePathUtilities.h69 IN CONST EFI_DEVICE_PATH_PROTOCOL *Src2
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEAsmPrinter.cpp154 MCOperand &Src2, MCOperand &RD, in emitBinary() argument
160 Inst.addOperand(Src2); in emitBinary()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcAsmPrinter.cpp136 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, in EmitBinary() argument
143 Inst.addOperand(Src2); in EmitBinary()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp70 Register Src2 = MI.getOperand(2).getReg(); in matchExtractVecEltPairwiseAdd() local
73 auto Cst = getIConstantVRegValWithLookThrough(Src2, MRI); in matchExtractVecEltPairwiseAdd()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DGISelKnownBits.cpp751 Register Src2 = MI.getOperand(2).getReg(); in computeNumSignBits() local
753 computeNumSignBits(Src2, DemandedElts, Depth + 1); in computeNumSignBits()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp1602 SDValue Src2 = Node->getOperand(2); in Select() local
1606 if (Src2.getValueType() != XLenVT) in Select()
1609 if (auto *C = dyn_cast<ConstantSDNode>(Src2)) { in Select()
1652 CurDAG->getMachineNode(VMSLTOpcode, DL, VT, {Src1, Src2, VL, SEW}), in Select()
1661 SDValue Src2 = Node->getOperand(3); in Select() local
1665 if (Src2.getValueType() != XLenVT) in Select()
1668 if (auto *C = dyn_cast<ConstantSDNode>(Src2)) { in Select()
1744 CurDAG->getMachineNode(VMSLTOpcode, DL, VT, {Src1, Src2, VL, SEW}), in Select()
1764 {MaskedOff, Src1, Src2, V0, VL, SEW, Glue}), in Select()

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