Home
last modified time | relevance | path

Searched refs:Src1RC (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.td2028 class getIns32 <RegisterOperand Src0RC, RegisterOperand Src1RC, int NumSrcArgs> {
2030 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
2035 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
2048 (ins Src1Mod:$src1_modifiers, Src1RC:$src1),
2049 (ins Src1RC:$src1)),
2071 class getInsVOP3Base<RegisterOperand Src0RC, RegisterOperand Src1RC,
2077 dag base = getIns64 <Src0RC, Src1RC, Src2RC, NumSrcArgs,
2085 class getInsVOP3P <RegisterOperand Src0RC, RegisterOperand Src1RC,
2089 dag base = getInsVOP3Base<Src0RC, Src1RC, Src2RC, NumSrcArgs,
2100 class getInsVOP3OpSel <RegisterOperand Src0RC, RegisterOperand Src1RC,
[all …]
H A DSIInstrInfo.cpp8344 const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg()); in splitScalarSMulU64() local
8350 RI.getSubRegisterClass(Src1RC, AMDGPU::sub0); in splitScalarSMulU64()
8359 buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC); in splitScalarSMulU64()
8363 buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC); in splitScalarSMulU64()
8453 const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg()); in splitScalarSMulPseudo() local
8459 RI.getSubRegisterClass(Src1RC, AMDGPU::sub0); in splitScalarSMulPseudo()
8468 buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC); in splitScalarSMulPseudo()
8519 const TargetRegisterClass *Src1RC = Src1.isReg() ? in splitScalar64BitBinaryOp() local
8524 RI.getSubRegisterClass(Src1RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
8528 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, in splitScalar64BitBinaryOp()
[all …]
H A DVOP1Instructions.td418 class VOP_MOVREL<RegisterOperand Src1RC> : VOPProfile<[untyped, i32, untyped, untyped]> {
423 let Ins32 = (ins Src0RC32:$vdst, Src1RC:$src0);
424 let Ins64 = (ins Src0RC64:$vdst, Src1RC:$src0);
H A DAMDGPUInstructionSelector.cpp919 const TargetRegisterClass *Src1RC = in selectG_INSERT() local
925 if (!Src0RC || !Src1RC) in selectG_INSERT()
930 !RBI.constrainGenericRegister(Src1Reg, *Src1RC, *MRI)) in selectG_INSERT()
H A DSIISelLowering.cpp5414 const TargetRegisterClass *Src1RC = Src1.isReg() in EmitInstrWithCustomInserter() local
5421 TRI->getSubRegisterClass(Src1RC, AMDGPU::sub1); in EmitInstrWithCustomInserter()
5426 MI, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC); in EmitInstrWithCustomInserter()
5431 MI, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC); in EmitInstrWithCustomInserter()
5656 const TargetRegisterClass *Src1RC = Src1.isReg() in EmitInstrWithCustomInserter() local
5663 TRI->getSubRegisterClass(Src1RC, AMDGPU::sub1); in EmitInstrWithCustomInserter()
5668 MI, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC); in EmitInstrWithCustomInserter()
5673 MI, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC); in EmitInstrWithCustomInserter()