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Searched refs:Src1RC (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.td1703 class getIns32 <RegisterOperand Src0RC, RegisterOperand Src1RC, int NumSrcArgs> {
1705 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1710 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
1740 Src1Mod:$src1_modifiers, Src1RC:$src1,
1743 Src1Mod:$src1_modifiers, Src1RC:$src1),
1748 (ins Src0RC:$src0, Src1RC:$src1, Clamp0:$clamp),
1749 (ins Src0RC:$src0, Src1RC:$src1))
1758 Src1Mod:$src1_modifiers, Src1RC:$src1,
1763 Src1Mod:$src1_modifiers, Src1RC:$src1,
1767 Src1Mod:$src1_modifiers, Src1RC:$src1,
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H A DVOP1Instructions.td378 class VOP_MOVREL<RegisterOperand Src1RC> : VOPProfile<[untyped, i32, untyped, untyped]> {
383 let Ins32 = (ins Src0RC32:$vdst, Src1RC:$src0);
384 let Ins64 = (ins Src0RC64:$vdst, Src1RC:$src0);
H A DSIInstrInfo.cpp7853 const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg()); in splitScalarSMulU64() local
7859 RI.getSubRegisterClass(Src1RC, AMDGPU::sub0); in splitScalarSMulU64()
7868 buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC); in splitScalarSMulU64()
7872 buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC); in splitScalarSMulU64()
7962 const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg()); in splitScalarSMulPseudo() local
7968 RI.getSubRegisterClass(Src1RC, AMDGPU::sub0); in splitScalarSMulPseudo()
7977 buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC); in splitScalarSMulPseudo()
8028 const TargetRegisterClass *Src1RC = Src1.isReg() ? in splitScalar64BitBinaryOp() local
8033 RI.getSubRegisterClass(Src1RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
8037 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, in splitScalar64BitBinaryOp()
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H A DAMDGPUInstructionSelector.cpp821 const TargetRegisterClass *Src1RC = in selectG_INSERT() local
827 if (!Src0RC || !Src1RC) in selectG_INSERT()
832 !RBI.constrainGenericRegister(Src1Reg, *Src1RC, *MRI)) in selectG_INSERT()
H A DSIISelLowering.cpp5075 const TargetRegisterClass *Src1RC = Src1.isReg() in EmitInstrWithCustomInserter() local
5082 TRI->getSubRegisterClass(Src1RC, AMDGPU::sub1); in EmitInstrWithCustomInserter()
5087 MI, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC); in EmitInstrWithCustomInserter()
5092 MI, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC); in EmitInstrWithCustomInserter()
5302 const TargetRegisterClass *Src1RC = Src1.isReg() in EmitInstrWithCustomInserter() local
5309 TRI->getSubRegisterClass(Src1RC, AMDGPU::sub1); in EmitInstrWithCustomInserter()
5314 MI, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC); in EmitInstrWithCustomInserter()
5319 MI, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC); in EmitInstrWithCustomInserter()