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Searched refs:Src0VT (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DVOPInstructions.td143 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
610 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
827 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
1072 !subst(P.Src0RC32, P.Src0VT,
1120 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
1121 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp));
1124 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0),
1129 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0),
1133 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))];
1143 dag src0_dag = (P.Src0VT (SrcPat P.Src0VT:$src0, i32:$src0_modifiers));
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H A DSIInstrInfo.td2182 class getHas64BitOps <int NumSrcArgs, ValueType DstVT, ValueType Src0VT,
2188 !if(!eq(Src0VT.Size, 64),
2199 class getHasSDWA <int NumSrcArgs, ValueType DstVT = i32, ValueType Src0VT = i32,
2205 !if(!eq(Src0VT.Size, 64),
2222 class getHasExt32BitDPP <int NumSrcArgs, ValueType DstVT = i32, ValueType Src0VT = i32,
2225 !not(getHas64BitOps<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret));
2228 class getHasExt64BitDPP <int NumSrcArgs, ValueType DstVT = i32, ValueType Src0VT = i32,
2231 getHas64BitOps<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret);
2235 class getHasExt <int NumSrcArgs, ValueType DstVT = i32, ValueType Src0VT = i32,
2238 getHasSDWA<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret);
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H A DVOP3PInstructions.td862 (P.Src0VT (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers)),
866 …(P.DstVT (Inst i32:$src0_modifiers, P.Src0VT:$src0, i32:$src1_modifiers, P.Src1VT:$src1, $src2_mod…
871 (P.Src0VT P.Src0VT:$src0),
875 …(P.DstVT (Inst (i32 8), P.Src0VT:$src0, (i32 8), P.Src1VT:$src1, i32:$src2_modifiers, P.Src2VT:$sr…
880 (VOP3PModsNeg i32:$src0_modifiers), (P.Src0VT P.Src0VT:$src0),
884 …(P.DstVT (Inst i32:$src0_modifiers, P.Src0VT:$src0, i32:$src1_modifiers, P.Src1VT:$src1, (i32 8), …
1087 …dag Src0InPat = !cond(IsAB_F16 : (ins (Src0VT (WMMAModsF16Neg Src0VT:$src0, i32:$src0_modifiers)…
1088 IsAB_BF16 : (ins Src0VT:$src0),
1089 IsIU : (ins (VOP3PModsNeg i32:$src0_modifiers), Src0VT:$src0),
1090 IsFP8BF8 : (ins Src0VT:$src0));
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H A DVOPCInstructions.td53 let HasExtDPP = getHasVOP3DPP<DstVT, Src0VT, Src1VT, Src2VT>.ret;
92 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
95 let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret;
111 let AsmVOP3Base = !if(Src0VT.isFP, "$src0_modifiers, $src1_modifiers$clamp",
122 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
125 let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret;
149 let ReadsModeReg = P.Src0VT.isFP;
258 (setcc (P.Src0VT
260 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
261 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
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H A DVOP2Instructions.td72 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
133 (node (P.Src0VT
135 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
136 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
138 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
440 (ins !if(!eq(Src0VT.Size, 32), VSrc_f32_Deferred, VSrc_f16_Deferred):$src0X,
489 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
492 let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret;
631 let Src0Mod = !if(!eq(Src0VT.Size, 16), FP16InputMods, FP32InputMods);
838 (DivergentBinFrag<Op> Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
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H A DVOP1Instructions.td52 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
111 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers))))],
113 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3OMods P.Src0VT:$src0,
115 [(set P.DstVT:$vdst, (node (P.Src0VT P.Src0RC32:$src0)))]
H A DVOP3Instructions.td998 dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2));
999 dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1));
1000 dag ret1 = (P.DstVT (node P.Src0VT:$src0));
1007 dag ret3 = (inst P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, (i1 0));
1008 dag ret2 = (inst P.Src0VT:$src0, P.Src1VT:$src1, (i1 0));
1009 dag ret1 = (inst P.Src0VT:$src0, (i1 0));
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp3296 EVT Src0VT = Src0.getValueType(); in SplitVecOp_VSELECT()
3306 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT); in SplitVecOp_VSELECT()
3319 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect); in SplitVecOp_VECREDUCE()
3292 EVT Src0VT = Src0.getValueType(); SplitVecOp_VSELECT() local