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Searched refs:Src0VT (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DVOPCInstructions.td53 let HasExtDPP = getHasVOP3DPP<DstVT, Src0VT, Src1VT, Src2VT>.ret;
95 let Src0RC32 = getVOPSrc0ForVT<Src0VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
97 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
100 let Src0ModDPP = getSrcModDPP_t16<Src0VT, 0/*IsFake16*/>.ret;
108 let Src0RC64 = getVOP3SrcForVT<Src0VT, 1/*IsTrue16*/>.ret;
111 let Src0Mod = getSrc0Mod<Src0VT, DstVT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
114 let Src0ModVOP3DPP = getSrc0ModVOP3DPP<Src0VT, DstVT, 0/*IsFake16*/>.ret;
121 let Src0RC32 = getVOPSrc0ForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
123 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
126 let Src0ModDPP = getSrcModDPP_t16<Src0VT, 1/*IsFake16*/>.ret;
[all …]
H A DVOPInstructions.td146 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
738 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
982 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
1269 !subst(P.Src0RC32, P.Src0VT,
1317 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
1318 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp));
1321 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0),
1326 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0),
1330 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))];
1340 dag src0_dag = (P.Src0VT (SrcPat P.Src0VT:$src0, i32:$src0_modifiers));
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H A DSIInstrInfo.td2466 class getHas64BitOps <int NumSrcArgs, ValueType DstVT, ValueType Src0VT,
2472 !if(!eq(Src0VT.Size, 64),
2483 class getHasSDWA <int NumSrcArgs, ValueType DstVT = i32, ValueType Src0VT = i32,
2489 !if(!eq(Src0VT.Size, 64),
2506 class getHasExt32BitDPP <int NumSrcArgs, ValueType DstVT = i32, ValueType Src0VT = i32,
2509 !not(getHas64BitOps<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret));
2512 class getHasExt64BitDPP <int NumSrcArgs, ValueType DstVT = i32, ValueType Src0VT = i32,
2515 getHas64BitOps<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret);
2519 class getHasExt <int NumSrcArgs, ValueType DstVT = i32, ValueType Src0VT = i32,
2522 getHasSDWA<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret);
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H A DVOP2Instructions.td86 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
149 (node (P.Src0VT
151 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
152 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
154 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
549 let Src0RC32 = getVOPSrc0ForVT<Src0VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
552 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
555 let Src0ModDPP = getSrcModDPP_t16<Src0VT, 0/*IsFake16*/>.ret;
568 let Src0RC64 = getVOP3SrcForVT<Src0VT, 1/*IsTrue16*/>.ret;
573 let Src0ModVOP3DPP = getSrc0ModVOP3DPP<Src0VT, DstVT, 0/*IsFake16*/>.ret;
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H A DVOP3PInstructions.td823 MFMA_F8F6F4_WithSizeTable<!srl(ps.Pfl.Src0VT.Size, 5),
1197 (P.Src0VT (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers)),
1201 …(P.DstVT (Inst i32:$src0_modifiers, P.Src0VT:$src0, i32:$src1_modifiers, P.Src1VT:$src1, $src2_mod…
1206 (P.Src0VT P.Src0VT:$src0),
1210 …(P.DstVT (Inst (i32 8), P.Src0VT:$src0, (i32 8), P.Src1VT:$src1, i32:$src2_modifiers, P.Src2VT:$sr…
1215 (VOP3PModsNeg i32:$src0_modifiers), (P.Src0VT P.Src0VT:$src0),
1219 …(P.DstVT (Inst i32:$src0_modifiers, P.Src0VT:$src0, i32:$src1_modifiers, P.Src1VT:$src1, (i32 8), …
1460 dag Src0InPat = !cond(IsAB_F32F64_IMod1 : (ins Src0VT:$src0),
1461 IsAB_F16BF16_IMod1 : (ins Src0VT:$src0),
1462 … IsAB_F16_IMod0 : (ins (Src0VT (WMMAModsF16Neg Src0VT:$src0, i32:$src0_modifiers))),
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H A DVOP3Instructions.td1127 let Src0RC64 = !if(!gt(P.Src0VT.Size, 32), getVOP3VRegSrcForVT<P.Src0VT>.ret,
1128 getVOP3SrcForVT<P.Src0VT>.ret);
1182 let Src0RC64 = !if(!gt(P.Src0VT.Size, 32), getVOP3VRegSrcForVT<P.Src0VT>.ret,
1183 getVOP3SrcForVT<P.Src0VT>.ret);
1639 dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2));
1640 dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1));
1641 dag ret1 = (P.DstVT (node P.Src0VT:$src0));
1648 dag ret3 = (inst P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, (i1 0));
1649 dag ret2 = (inst P.Src0VT:$src0, P.Src1VT:$src1, (i1 0));
1650 dag ret1 = (inst P.Src0VT:$src0, (i1 0));
H A DVOP1Instructions.td52 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
113 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers))))],
115 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3OMods P.Src0VT:$src0,
117 [(set P.DstVT:$vdst, (node (P.Src0VT P.Src0RC32:$src0)))]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp3584 EVT Src0VT = Src0.getValueType(); in SplitVecOp_VSELECT() local
3594 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT); in SplitVecOp_VSELECT()
3607 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect); in SplitVecOp_VSELECT()