Searched refs:Src0Ty (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MIPatternMatch.h | 726 template <typename Src0Ty, typename Src1Ty, typename Src2Ty, unsigned Opcode>
728 Src0Ty Src0;
732 TernaryOp_match(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2)
747 template <typename Src0Ty, typename Src1Ty, typename Src2Ty>
748 inline TernaryOp_match<Src0Ty, Src1Ty, Src2Ty,
750 m_GInsertVecElt(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) {
751 return TernaryOp_match<Src0Ty, Src1Ty, Src2Ty,
755 template <typename Src0Ty, typename Src1Ty, typename Src2Ty>
756 inline TernaryOp_match<Src0Ty, Src1Ty, Src2Ty, TargetOpcode::G_SELECT>
757 m_GISelect(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) {
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineVerifier.cpp | 1713 LLT Src0Ty = MRI->getType(Src0Op.getReg()); in verifyPreISelGenericInstruction() local
1721 if (!Src0Ty.isVector()) { in verifyPreISelGenericInstruction()
1731 if (DstTy != Src0Ty) { in verifyPreISelGenericInstruction()
1736 if (Src0Ty.getElementType() != Src1Ty.getElementType()) { in verifyPreISelGenericInstruction()
1799 LLT Src0Ty = MRI->getType(MI->getOperand(1).getReg()); in verifyPreISelGenericInstruction() local
1802 if (Src0Ty != Src1Ty) in verifyPreISelGenericInstruction()
1805 if (Src0Ty.getScalarType() != DstTy.getScalarType()) in verifyPreISelGenericInstruction()
1810 int SrcNumElts = Src0Ty.isVector() ? Src0Ty.getNumElements() : 1; in verifyPreISelGenericInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 7307 auto [Dst, DstTy, Src0, Src0Ty, Src1, Src1Ty] = MI.getFirst3RegLLTs(); in lowerFCopySign()
7308 const int Src0Size = Src0Ty.getScalarSizeInBits(); in lowerFCopySign()
7312 Src0Ty, APInt::getSignMask(Src0Size)); in lowerFCopySign()
7315 Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1)); in lowerFCopySign()
7317 Register And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask).getReg(0); in lowerFCopySign()
7319 if (Src0Ty == Src1Ty) { in lowerFCopySign()
7322 auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size); in lowerFCopySign()
7323 auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1); in lowerFCopySign()
7324 auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt); in lowerFCopySign()
7325 And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask).getReg(0); in lowerFCopySign()
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