Searched refs:Src0Regs (Results 1 – 2 of 2) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 2112 SmallVector<Register, 2> Src0Regs(OpdMapper.getVRegs(1)); in applyMappingSMULU64() local
2117 assert(Src0Regs.empty() && Src1Regs.empty()); in applyMappingSMULU64()
2123 assert(Src0Regs.size() == Src1Regs.size() && in applyMappingSMULU64()
2124 (Src0Regs.empty() || Src0Regs.size() == 2)); in applyMappingSMULU64()
2135 if (Src0Regs.empty()) in applyMappingSMULU64()
2136 split64BitValueForMapping(B, Src0Regs, HalfTy, MI.getOperand(1).getReg()); in applyMappingSMULU64()
2138 setRegsToType(MRI, Src0Regs, HalfTy); in applyMappingSMULU64()
2165 Register Hi = B.buildUMulH(HalfTy, Src0Regs[0], Src1Regs[0]).getReg(0); in applyMappingSMULU64()
2166 Register MulLoHi = B.buildMul(HalfTy, Src0Regs[0], Src1Regs[1]).getReg(0); in applyMappingSMULU64()
2168 Register MulHiLo = B.buildMul(HalfTy, Src0Regs[1], Src1Regs[0]).getReg(0); in applyMappingSMULU64()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 6184 SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs; in narrowScalarBasic() local
6188 Src0Regs, Src0LeftoverRegs, MIRBuilder, MRI)) in narrowScalarBasic()
6198 {Src0Regs[I], Src1Regs[I]}); in narrowScalarBasic()
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