| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 4635 Register Src0Reg = getRegForValue(I->getOperand(0)); in selectRem() local
4636 if (!Src0Reg) in selectRem()
4645 Register QuotReg = fastEmitInst_rr(DivOpc, RC, Src0Reg, Src1Reg); in selectRem()
4649 Register ResultReg = fastEmitInst_rrr(MSubOpc, RC, QuotReg, Src1Reg, Src0Reg); in selectRem()
4694 Register Src0Reg = getRegForValue(Src0); in selectMul() local
4695 if (!Src0Reg) in selectMul()
4699 emitLSL_ri(VT, SrcVT, Src0Reg, ShiftVal, IsZExt); in selectMul()
4707 Register Src0Reg = getRegForValue(I->getOperand(0)); in selectMul() local
4708 if (!Src0Reg) in selectMul()
4715 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src1Reg); in selectMul()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.h | 269 unsigned Src0Reg,
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| H A D | AMDGPUInstructionSelector.cpp | 436 Register Src0Reg = I.getOperand(2).getReg(); in selectG_UADDO_USUBO_UADDE_USUBE() local
461 !RBI.constrainGenericRegister(Src0Reg, AMDGPU::SReg_32RegClass, *MRI) || in selectG_UADDO_USUBO_UADDE_USUBE()
790 Register Src0Reg = I.getOperand(1).getReg(); in selectG_INSERT() local
817 const RegisterBank *Src0Bank = RBI.getRegBank(Src0Reg, *MRI, TRI); in selectG_INSERT()
831 !RBI.constrainGenericRegister(Src0Reg, *Src0RC, *MRI) || in selectG_INSERT()
837 .addReg(Src0Reg) in selectG_INSERT()
1026 Register Src0Reg = I.getOperand(2).getReg(); in selectG_INTRINSIC() local
1031 for (Register Reg : { DstReg, Src0Reg, Src1Reg }) in selectG_INTRINSIC()
1377 Register Src0Reg = in selectIntrinsicCmp() local
1384 SelectedMI.addReg(Src0Reg); in selectIntrinsicCmp()
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| H A D | R600InstrInfo.cpp | 1213 unsigned Src0Reg, in buildDefaultInstruction() argument
1226 .addReg(Src0Reg) // $src0 in buildDefaultInstruction()
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| H A D | AMDGPULegalizerInfo.cpp | 2480 Register Src0Reg = MI.getOperand(1).getReg(); in legalizeFrem() local
2485 auto Div = B.buildFDiv(Ty, Src0Reg, Src1Reg, Flags); in legalizeFrem()
2488 B.buildFMA(DstReg, Neg, Src1Reg, Src0Reg, Flags); in legalizeFrem()
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| H A D | AMDGPURegisterBankInfo.cpp | 4610 Register Src0Reg = MI.getOperand(2).getReg(); in getInstrMapping() local
4612 unsigned Src0Size = MRI.getType(Src0Reg).getSizeInBits(); in getInstrMapping()
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| H A D | SIInstrInfo.cpp | 5947 Register Src0Reg = Src0.getReg(); in legalizeOperandsVOP2() local
5959 Src1.ChangeToRegister(Src0Reg, false, false, Src0Kill); in legalizeOperandsVOP2()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1932 Register Src0Reg = getRegForValue(I->getOperand(0)); in selectDivRem() local
1934 if (!Src0Reg || !Src1Reg) in selectDivRem()
1937 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg); in selectDivRem()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 7451 auto [DstReg, DstTy, Src0Reg, Src0Ty] = MI.getFirst2RegLLTs(); in lowerMergeValues()
7455 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0); in lowerMergeValues()
7600 auto [DstReg, DstTy, Src0Reg, Src0Ty, Src1Reg, Src1Ty] = in lowerShuffleVector()
7618 BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg); in lowerShuffleVector()
7621 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; in lowerShuffleVector()
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