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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h1208 MachineInstrBuilder buildInsertSubvector(const DstOp &Res, const SrcOp &Src0,
1814 MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1817 return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1831 MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1834 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1847 MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1850 return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1862 MachineInstrBuilder buildAbds(const DstOp &Dst, const SrcOp &Src0, in buildAbds() argument
1864 return buildInstr(TargetOpcode::G_ABDS, {Dst}, {Src0, Src1}); in buildAbds()
1876 MachineInstrBuilder buildAbdu(const DstOp &Dst, const SrcOp &Src0, in buildAbdu() argument
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H A DMIPatternMatch.h859 Src0Ty Src0;
863 TernaryOp_match(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2)
864 : Src0(Src0), Src1(Src1), Src2(Src2) {}
870 return (Src0.match(MRI, TmpMI->getOperand(1).getReg()) &&
881 m_GInsertVecElt(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) {
883 TargetOpcode::G_INSERT_VECTOR_ELT>(Src0, Src1, Src2);
888 m_GISelect(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) {
890 Src0, Src1, Src2);
H A DGISelValueTracking.h43 void computeKnownBitsMin(Register Src0, Register Src1, KnownBits &Known,
46 unsigned computeNumSignBitsMin(Register Src0, Register Src1,
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ExpandSpecialInstrs.cpp147 Register Src0 = in runOnMachineFunction() local
153 (void) Src0; in runOnMachineFunction()
155 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 && in runOnMachineFunction()
157 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1)); in runOnMachineFunction()
199 Register Src0 = in runOnMachineFunction() local
212 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
218 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
219 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction()
253 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1); in runOnMachineFunction()
H A DAMDGPUInstCombineIntrinsic.cpp46 static APFloat fmed3AMDGCN(const APFloat &Src0, const APFloat &Src1, in fmed3AMDGCN() argument
48 APFloat Max3 = maxnum(maxnum(Src0, Src1), Src2); in fmed3AMDGCN()
50 APFloat::cmpResult Cmp0 = Max3.compare(Src0); in fmed3AMDGCN()
58 return maxnum(Src0, Src2); in fmed3AMDGCN()
60 return maxnum(Src0, Src1); in fmed3AMDGCN()
804 Value *Src0 = II.getArgOperand(0); in instCombineIntrinsic() local
809 II.getModule(), Intrinsic::is_fpclass, Src0->getType())); in instCombineIntrinsic()
818 if (isa<PoisonValue>(Src0) || isa<PoisonValue>(Src1)) in instCombineIntrinsic()
826 if (IC.getSimplifyQuery().isUndefValue(Src0)) { in instCombineIntrinsic()
859 if (Value *Src0 = foldFPTruncToF16RTZ(II.getArgOperand(0))) { in instCombineIntrinsic() local
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H A DSIShrinkInstructions.cpp103 MachineOperand &Src0 = MI.getOperand(Src0Idx); in foldImmediates() local
104 if (Src0.isReg()) { in foldImmediates()
105 Register Reg = Src0.getReg(); in foldImmediates()
114 Src0.ChangeToImmediate(MovSrc.getImm()); in foldImmediates()
117 Src0.ChangeToFrameIndex(MovSrc.getIndex()); in foldImmediates()
120 Src0.ChangeToGA(MovSrc.getGlobal(), MovSrc.getOffset(), in foldImmediates()
254 const MachineOperand &Src0 = MI.getOperand(0); in shrinkScalarCompare() local
255 if (!Src0.isReg()) in shrinkScalarCompare()
428 MachineOperand &Src0 = *TII->getNamedOperand(MI, AMDGPU::OpName::src0); in shrinkMadFma() local
439 else if (Src0.isReg() && TRI->isVGPR(*MRI, Src0.getReg())) in shrinkMadFma()
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H A DGCNVOPDUtils.cpp91 const MachineOperand &Src0 = *TII.getNamedOperand(MI, AMDGPU::OpName::src0); in checkVOPDRegConstraints() local
92 if (Src0.isReg()) { in checkVOPDRegConstraints()
93 if (!TRI->isVectorRegister(MRI, Src0.getReg())) { in checkVOPDRegConstraints()
94 if (!is_contained(UniqueScalarRegs, Src0.getReg())) in checkVOPDRegConstraints()
95 UniqueScalarRegs.push_back(Src0.getReg()); in checkVOPDRegConstraints()
97 } else if (!TII.isInlineConstant(Src0)) { in checkVOPDRegConstraints()
100 addLiteral(Src0); in checkVOPDRegConstraints()
H A DSIOptimizeExecMasking.cpp555 MachineOperand &Src0 = SaveExecInst->getOperand(1); in optimizeExecSequence() local
560 if (Src0.isReg() && Src0.getReg() == CopyFromExec) { in optimizeExecSequence()
566 OtherOp = &Src0; in optimizeExecSequence()
602 MachineOperand *Src0 = TII->getNamedOperand(VCmp, AMDGPU::OpName::src0); in optimizeVCMPSaveExecSequence() local
628 Builder.add(*Src0); in optimizeVCMPSaveExecSequence()
638 if (Src0->isReg()) in optimizeVCMPSaveExecSequence()
639 MRI->clearKillFlags(Src0->getReg()); in optimizeVCMPSaveExecSequence()
702 MachineOperand *Src0 = TII->getNamedOperand(*VCmp, AMDGPU::OpName::src0); in tryRecordVCmpxAndSaveexecSequence() local
703 if (Src0->isReg() && TRI->isSGPRReg(*MRI, Src0->getReg()) && in tryRecordVCmpxAndSaveexecSequence()
704 MI.modifiesRegister(Src0->getReg(), TRI)) in tryRecordVCmpxAndSaveexecSequence()
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H A DGCNDPPCombine.cpp296 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); in createDPPInst() local
297 assert(Src0); in createDPPInst()
299 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) { in createDPPInst()
304 DPPInst.add(*Src0); in createDPPInst()
687 auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0); in combineDPPMov() local
689 if (Use != Src0 && !(Use == Src1 && OrigMI.isCommutable())) { // [1] in combineDPPMov()
695 assert(Src0 && "Src1 without Src0?"); in combineDPPMov()
696 if ((Use == Src0 && ((Src1 && Src1->isIdenticalTo(*Src0)) || in combineDPPMov()
697 (Src2 && Src2->isIdenticalTo(*Src0)))) || in combineDPPMov()
698 (Use == Src1 && (Src1->isIdenticalTo(*Src0) || in combineDPPMov()
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H A DAMDGPUCombinerHelper.cpp426 Register Src0, in matchExpandPromotedF16FMed3() argument
434 return isFPExtFromF16OrConst(MRI, Src0) && isFPExtFromF16OrConst(MRI, Src1) && in matchExpandPromotedF16FMed3()
439 Register Src0, in applyExpandPromotedF16FMed3() argument
444 Src0 = Builder.buildFPTrunc(LLT::scalar(16), Src0).getReg(0); in applyExpandPromotedF16FMed3()
448 LLT Ty = MRI.getType(Src0); in applyExpandPromotedF16FMed3()
449 auto A1 = Builder.buildFMinNumIEEE(Ty, Src0, Src1); in applyExpandPromotedF16FMed3()
450 auto B1 = Builder.buildFMaxNumIEEE(Ty, Src0, Src1); in applyExpandPromotedF16FMed3()
H A DAMDGPUPostLegalizerCombiner.cpp324 Register Src0; in matchCvtF32UByteN() local
326 IsShr = mi_match(SrcReg, MRI, m_GLShr(m_Reg(Src0), m_ICst(ShiftAmt))); in matchCvtF32UByteN()
327 if (IsShr || mi_match(SrcReg, MRI, m_GShl(m_Reg(Src0), m_ICst(ShiftAmt)))) { in matchCvtF32UByteN()
336 MatchInfo.CvtVal = Src0; in matchCvtF32UByteN()
419 Register Src0 = MI.getOperand(1).getReg(); in matchCombine_s_mul_u64() local
421 if (MRI.getType(Src0) != LLT::scalar(64)) in matchCombine_s_mul_u64()
425 VT->getKnownBits(Src0).countMinLeadingZeros() >= 32) { in matchCombine_s_mul_u64()
431 VT->computeNumSignBits(Src0) >= 33) { in matchCombine_s_mul_u64()
H A DSIInstrInfo.cpp1352 const MachineOperand &Src0 = MI.getOperand(1); in getConstValDefinedInReg() local
1353 if (Src0.isImm()) { in getConstValDefinedInReg()
1354 ImmVal = Src0.getImm(); in getConstValDefinedInReg()
1363 const MachineOperand &Src0 = MI.getOperand(1); in getConstValDefinedInReg() local
1364 if (Src0.isImm()) { in getConstValDefinedInReg()
1365 ImmVal = static_cast<int64_t>(reverseBits<int32_t>(Src0.getImm())); in getConstValDefinedInReg()
1374 const MachineOperand &Src0 = MI.getOperand(1); in getConstValDefinedInReg() local
1375 if (Src0.isImm()) { in getConstValDefinedInReg()
1376 ImmVal = static_cast<int64_t>(~static_cast<int32_t>(Src0.getImm())); in getConstValDefinedInReg()
2724 bool SIInstrInfo::swapSourceModifiers(MachineInstr &MI, MachineOperand &Src0, in swapSourceModifiers() argument
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H A DSIPeepholeSDWA.cpp708 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
709 auto Imm = foldToImm(*Src0); in matchSDWAOperand()
750 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
751 auto Imm = foldToImm(*Src0); in matchSDWAOperand()
819 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
822 if (!Src0->isReg() || Src0->getReg().isPhysical() || in matchSDWAOperand()
827 Src0, Dst, SrcSel, false, false, Opcode != AMDGPU::V_BFE_U32_e64); in matchSDWAOperand()
836 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
839 auto Imm = foldToImm(*Src0); in matchSDWAOperand()
843 ValSrc = Src0; in matchSDWAOperand()
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H A DAMDGPUCombinerHelper.h38 bool matchExpandPromotedF16FMed3(MachineInstr &MI, Register Src0,
40 void applyExpandPromotedF16FMed3(MachineInstr &MI, Register Src0,
H A DSIFoldOperands.cpp387 MachineOperand *Src0 = &Def->getOperand(1); in foldCopyToVGPROfScalarAddOfFrameIndex() local
393 if (!Src0->isFI() && !Src1->isFI()) in foldCopyToVGPROfScalarAddOfFrameIndex()
396 if (Src0->isFI()) in foldCopyToVGPROfScalarAddOfFrameIndex()
397 std::swap(Src0, Src1); in foldCopyToVGPROfScalarAddOfFrameIndex()
399 const bool UseVOP3 = !Src0->isImm() || TII->isInlineConstant(*Src0); in foldCopyToVGPROfScalarAddOfFrameIndex()
417 Add.add(*Src0).add(*Src1).setMIFlags(Def->getFlags()); in foldCopyToVGPROfScalarAddOfFrameIndex()
433 .add(*Src0) in foldCopyToVGPROfScalarAddOfFrameIndex()
1558 MachineOperand *Src0 = &MI->getOperand(Src0Idx); in tryConstantFoldOp() local
1559 std::optional<int64_t> Src0Imm = getImmOrMaterializedImm(*Src0); in tryConstantFoldOp()
1601 std::swap(Src0, Src1); in tryConstantFoldOp()
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H A DAMDGPURegBankCombiner.cpp316 MachineInstr *Src0 = getDefIgnoringCopies(MI.getOperand(1).getReg(), MRI); in matchFPMed3ToClamp() local
320 if (isFCst(Src0) && !isFCst(Src1)) in matchFPMed3ToClamp()
321 std::swap(Src0, Src1); in matchFPMed3ToClamp()
324 if (isFCst(Src0) && !isFCst(Src1)) in matchFPMed3ToClamp()
325 std::swap(Src0, Src1); in matchFPMed3ToClamp()
329 Register Val = Src0->getOperand(0).getReg(); in matchFPMed3ToClamp()
H A DSIISelLowering.cpp5308 MachineOperand &Src0 = MI.getOperand(2); in EmitInstrWithCustomInserter() local
5316 .add(Src0) in EmitInstrWithCustomInserter()
5335 MachineOperand &Src0 = MI.getOperand(1); in EmitInstrWithCustomInserter() local
5342 .add(Src0) in EmitInstrWithCustomInserter()
5353 MI, MRI, Src0, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter()
5355 MI, MRI, Src0, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter()
5389 MachineOperand &Src0 = MI.getOperand(1); in EmitInstrWithCustomInserter() local
5395 .add(Src0) in EmitInstrWithCustomInserter()
5411 const TargetRegisterClass *Src0RC = Src0.isReg() in EmitInstrWithCustomInserter()
5412 ? MRI.getRegClass(Src0.getReg()) in EmitInstrWithCustomInserter()
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H A DSIFixSGPRCopies.cpp724 MachineOperand &Src0 = MI.getOperand(Src0Idx); in run() local
728 if ((Src0.isReg() && TRI->isSGPRReg(*MRI, Src0.getReg()) && in run()
729 Src0.getReg() != AMDGPU::M0) && in run()
738 for (MachineOperand *MO : {&Src0, &Src1}) { in run()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/
H A DAMDGPU.cpp32 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); in emitBinaryExpMaybeConstrainedFPBuiltin() local
38 {Src0->getType(), Src1->getType()}); in emitBinaryExpMaybeConstrainedFPBuiltin()
39 return CGF.Builder.CreateConstrainedFPCall(F, {Src0, Src1}); in emitBinaryExpMaybeConstrainedFPBuiltin()
43 CGF.CGM.getIntrinsic(IntrinsicID, {Src0->getType(), Src1->getType()}); in emitBinaryExpMaybeConstrainedFPBuiltin()
44 return CGF.Builder.CreateCall(F, {Src0, Src1}); in emitBinaryExpMaybeConstrainedFPBuiltin()
188 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); in emitFPIntBuiltin() local
191 Function *F = CGF.CGM.getIntrinsic(IntrinsicID, Src0->getType()); in emitFPIntBuiltin()
192 return CGF.Builder.CreateCall(F, {Src0, Src1}); in emitFPIntBuiltin()
330 llvm::Value *Src0 = EmitScalarExpr(E->getArg(0)); in EmitAMDGPUBuiltinExpr() local
336 Src0->getType()); in EmitAMDGPUBuiltinExpr()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCExpandAtomicPseudoInsts.cpp50 Register Dest0, Register Dest1, Register Src0, in PairedCopy() argument
54 if (Dest0 == Src1 && Dest1 == Src0) { in PairedCopy()
59 } else if (Dest0 != Src0 || Dest1 != Src1) { in PairedCopy()
60 if (Dest0 == Src1 || Dest1 != Src0) { in PairedCopy()
62 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0); in PairedCopy()
64 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0); in PairedCopy()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp296 unsigned Src0 = 0, SubReg0; in transformInstruction() local
307 Src0 = MOSrc0->getReg(); in transformInstruction()
339 if (!Src0) { in transformInstruction()
341 Src0 = MRI->createVirtualRegister(&AArch64::FPR64RegClass); in transformInstruction()
342 insertCopy(TII, MI, Src0, OrigSrc0, KillSrc0); in transformInstruction()
361 .addReg(Src0, getKillRegState(KillSrc0), SubReg0) in transformInstruction()
/freebsd/contrib/llvm-project/clang/lib/Headers/hlsl/
H A Dhlsl_intrinsics.h205 const inline half4 dst(half4 Src0, half4 Src1) { in dst() argument
206 return __detail::dst_impl(Src0, Src1); in dst()
209 const inline float4 dst(float4 Src0, float4 Src1) { in dst() argument
210 return __detail::dst_impl(Src0, Src1); in dst()
213 const inline double4 dst(double4 Src0, double4 Src1) { in dst() argument
214 return __detail::dst_impl(Src0, Src1); in dst()
H A Dhlsl_intrinsic_helpers.h39 constexpr vector<T, 4> dst_impl(vector<T, 4> Src0, vector<T, 4> Src1) { in dst_impl() argument
40 return {1, Src0[1] * Src1[1], Src0[2], Src1[3]}; in dst_impl()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineCalls.cpp962 Value *Src0 = II.getArgOperand(0); in foldIntrinsicIsFPClass() local
975 if (match(Src0, m_FNeg(m_Value(FNegSrc)))) { in foldIntrinsicIsFPClass()
983 if (match(Src0, m_FAbs(m_Value(FAbsSrc)))) { in foldIntrinsicIsFPClass()
994 Constant *Inf = ConstantFP::getInfinity(Src0->getType()); in foldIntrinsicIsFPClass()
1000 Value *Fabs = Builder.CreateUnaryIntrinsic(Intrinsic::fabs, Src0); in foldIntrinsicIsFPClass()
1013 ConstantFP::getInfinity(Src0->getType(), OrderedMask == fcNegInf); in foldIntrinsicIsFPClass()
1014 Value *EqInf = IsUnordered ? Builder.CreateFCmpUEQ(Src0, Inf) in foldIntrinsicIsFPClass()
1015 : Builder.CreateFCmpOEQ(Src0, Inf); in foldIntrinsicIsFPClass()
1027 Constant *Inf = ConstantFP::getInfinity(Src0->getType(), in foldIntrinsicIsFPClass()
1029 Value *NeInf = IsUnordered ? Builder.CreateFCmpUNE(Src0, Inf) in foldIntrinsicIsFPClass()
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DScalarizeMaskedMemIntrin.cpp151 Value *Src0 = CI->getArgOperand(3); in scalarizeMaskedLoad() local
181 Value *VResult = Src0; in scalarizeMaskedLoad()
217 Phi->addIncoming(Src0, IfBlock); in scalarizeMaskedLoad()
477 Value *Src0 = CI->getArgOperand(3); in scalarizeMaskedGather() local
491 Value *VResult = Src0; in scalarizeMaskedGather()

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