| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatterns.td | 372 def Add: pf2<add>; def And: pf2<and>; def Sra: pf2<sra>;
1185 def: OpR_RI_pat<S2_asr_i_r, Sra, i32, I32, u5_0ImmPred>;
1188 def: OpR_RI_pat<S2_asr_i_p, Sra, i64, I64, u6_0ImmPred>;
1191 def: OpR_RI_pat<S2_asr_i_vh, Sra, v4i16, V4I16, u4_0ImmPred>;
1194 def: OpR_RI_pat<S2_asr_i_vh, Sra, v2i32, V2I32, u5_0ImmPred>;
1198 def: OpR_RR_pat<S2_asr_r_r, Sra, i32, I32, I32>;
1201 def: OpR_RR_pat<S2_asr_r_p, Sra, i64, I64, I32>;
1301 def: AccRRI_pat<S2_asr_i_r_acc, Add, Su<Sra>, I32, u5_0ImmPred>;
1302 def: AccRRI_pat<S2_asr_i_r_nac, Sub, Su<Sra>, I32, u5_0ImmPred>;
1303 def: AccRRI_pat<S2_asr_i_r_and, And, Su<Sra>, I32, u5_0ImmPred>;
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 4818 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Add, C1); in visitSDIVLike() local
4819 AddToWorklist(Sra.getNode()); in visitSDIVLike()
4828 Sra = DAG.getSelect(DL, VT, IsOneOrAllOnes, N0, Sra); in visitSDIVLike()
4833 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, Zero, Sra); in visitSDIVLike()
4837 SDValue Res = DAG.getSelect(DL, VT, IsNeg, Sub, Sra); in visitSDIVLike()
11346 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, X, ShAmtC); in foldSelectOfConstantsUsingSra() local
11347 return DAG.getNode(ISD::OR, DL, VT, Sra, C1); in foldSelectOfConstantsUsingSra()
11352 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, X, ShAmtC); in foldSelectOfConstantsUsingSra() local
11353 return DAG.getNode(ISD::AND, DL, VT, Sra, C1); in foldSelectOfConstantsUsingSra()
11564 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); in foldVSelectToSignBitSplatMask() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 14049 SDValue Sra = DAG.getNode(ISD::SRA, DL, HalfVT, Cast, in combineVectorMulToSraBitcast()
14051 return DAG.getNode(ISD::BITCAST, DL, VT, Sra); in performMULCombine()
14046 SDValue Sra = DAG.getNode(ISD::SRA, DL, HalfVT, Cast, combineVectorMulToSraBitcast() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 28167 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, X, ShiftAmt); in LowerADDSAT_SUBSAT() local
28168 return DAG.getNode(ISD::AND, DL, VT, Xor, Sra); in LowerADDSAT_SUBSAT()
49419 SDValue Sra = in combineAndMaskToShift() local
49422 return DAG.getNode(X86ISD::ANDNP, DL, VT, Sra, Y); in combineAndMaskToShift()
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