Searched refs:SplitLoad (Results 1 – 4 of 4) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegBankLegalizeRules.cpp | 674 .Any({{{UniB256, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB256}, {VgprP1}, SplitLoad}}) in RegBankLegalizeRules()
675 .Any({{{UniB512, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB512}, {VgprP1}, SplitLoad}}) in RegBankLegalizeRules()
681 .Any({{{DivB256, DivP4}}, {{VgprB256}, {VgprP4}, SplitLoad}}) in RegBankLegalizeRules()
685 ….Any({{{UniB96, UniP4}, isAlign4 && !isAlign16 && isUL}, {{SgprB96}, {SgprP4}, SplitLoad}}, !hasUn… in RegBankLegalizeRules()
691 .Any({{{UniB256, UniP4}, !isAlign4 || !isUL}, {{UniInVgprB256}, {VgprP4}, SplitLoad}}) in RegBankLegalizeRules()
692 .Any({{{UniB512, UniP4}, !isAlign4 || !isUL}, {{UniInVgprB512}, {VgprP4}, SplitLoad}}) in RegBankLegalizeRules()
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| H A D | AMDGPURegBankLegalizeRules.h | 218 SplitLoad, enumerator
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| H A D | AMDGPURegBankLegalizeHelper.cpp | 480 case SplitLoad: { in lower()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 13960 SDValue SplitLoad = in CombineExtLoad() local
13968 Loads.push_back(SplitLoad.getValue(0)); in CombineExtLoad()
13969 Chains.push_back(SplitLoad.getValue(1)); in CombineExtLoad()
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